diff --git a/boards/panels/explorer-both/.explorer-both.kicad_dru b/boards/panels/explorer-both/.explorer-both.kicad_dru new file mode 100644 index 0000000..8c52961 --- /dev/null +++ b/boards/panels/explorer-both/.explorer-both.kicad_dru @@ -0,0 +1,178 @@ +(version 1) + +(rule "Board_0-Minimum Trace Width (outer layer)" + (constraint track_width (min 5mil)) + (layer outer) + (condition "A.Type == 'track'")) + +(rule "Board_0-Minimum Trace Spacing (outer layer)" + (constraint clearance (min 5mil)) + (layer outer) + (condition "A.Type == 'track' && B.Type == A.Type")) + +(rule "Board_0-Minimum Trace Width and Spacing (inner layer)" + (constraint track_width (min 3.5mil)) + (layer inner) + (condition "A.Type == 'track'")) + +(rule "Board_0-Minimum Trace Spacing (inner layer)" + (constraint clearance (min 3.5mil)) + (layer inner) + (condition "A.Type == 'track' && B.Type == A.Type")) + +(rule "Board_0-Minimum Text" + (constraint text_thickness (min 0.15mm)) + (constraint text_height (min 1mm)) + (layer "?.Silkscreen")) + +(rule "Board_0-Pad to Silkscreen" + (constraint silk_clearance (min 0.15mm)) + (layer outer) + (condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')")) + +(rule "Board_0-Trace to Outline" + (constraint edge_clearance (min 0.3mm)) + (condition "A.Type == 'track'")) + +(rule "Board_0-drill hole size (mechanical)" + (constraint hole_size (min 0.2mm) (max 6.3mm))) + +(rule "Board_0-Minimum Via Hole Size" + (constraint hole_size (min 0.2mm)) + (condition "A.Type == 'via'")) + +(rule "Board_0-Minimum Via Diameter" + (constraint via_diameter (min 0.45mm)) + (condition "A.Type == 'via'")) + +(rule "Board_0-PTH Hole Size" + (constraint hole_size (min 0.2mm) (max 6.35mm)) + (condition "A.isPlated()")) + +(rule "Board_0-Minimum Non-plated Hole Size" + (constraint hole_size (min 0.5mm)) + (condition "A.Type == 'pad' && !A.isPlated()")) + +(rule "Board_0-Minimum Castellated Hole Size" + (constraint hole_size (min 0.6mm)) + (condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")) + +(rule "Board_0-hole to hole clearance (different nets)" + (constraint hole_to_hole (min 0.5mm)) + (condition "A.Net != B.Net")) + +(rule "Board_0-via to track clearance" + (constraint hole_clearance (min 0.254mm)) + (condition "A.Type == 'via' && B.Type == 'track'")) + +(rule "Board_0-via to via clearance (same nets)" + (constraint hole_to_hole (min 0.254mm)) + (condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net")) + +(rule "Board_0-pad to pad clearance (with hole, different nets)" + (constraint hole_to_hole (min 0.5mm)) + (condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net")) + +(rule "Board_0-pad to pad clearance (without hole, different nets)" + (constraint clearance (min 0.127mm)) + (condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net")) + +(rule "Board_0-NPTH to Track clearance)" + (constraint hole_clearance (min 0.254mm)) + (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'")) + +(rule "Board_0-PTH to Track clearance)" + (constraint hole_clearance (min 0.33mm)) + (condition "A.isPlated() && B.Type == 'track'")) + +(rule "Board_0-Pad to Track clearance)" + (constraint clearance (min 0.2mm)) + (condition "A.isPlated() && B.Type == 'track'")) +(rule "Board_1-Minimum Trace Width (outer layer)" + (constraint track_width (min 5mil)) + (layer outer) + (condition "A.Type == 'track'")) + +(rule "Board_1-Minimum Trace Spacing (outer layer)" + (constraint clearance (min 5mil)) + (layer outer) + (condition "A.Type == 'track' && B.Type == A.Type")) + +(rule "Board_1-Minimum Trace Width and Spacing (inner layer)" + (constraint track_width (min 3.5mil)) + (layer inner) + (condition "A.Type == 'track'")) + +(rule "Board_1-Minimum Trace Spacing (inner layer)" + (constraint clearance (min 3.5mil)) + (layer inner) + (condition "A.Type == 'track' && B.Type == A.Type")) + +(rule "Board_1-Minimum Text" + (constraint text_thickness (min 0.15mm)) + (constraint text_height (min 1mm)) + (layer "?.Silkscreen")) + +(rule "Board_1-Pad to Silkscreen" + (constraint silk_clearance (min 0.15mm)) + (layer outer) + (condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')")) + +(rule "Board_1-Trace to Outline" + (constraint edge_clearance (min 0.3mm)) + (condition "A.Type == 'track'")) + +(rule "Board_1-drill hole size (mechanical)" + (constraint hole_size (min 0.2mm) (max 6.3mm))) + +(rule "Board_1-Minimum Via Hole Size" + (constraint hole_size (min 0.2mm)) + (condition "A.Type == 'via'")) + +(rule "Board_1-Minimum Via Diameter" + (constraint via_diameter (min 0.45mm)) + (condition "A.Type == 'via'")) + +(rule "Board_1-PTH Hole Size" + (constraint hole_size (min 0.2mm) (max 6.35mm)) + (condition "A.isPlated()")) + +(rule "Board_1-Minimum Non-plated Hole Size" + (constraint hole_size (min 0.5mm)) + (condition "A.Type == 'pad' && !A.isPlated()")) + +(rule "Board_1-Minimum Castellated Hole Size" + (constraint hole_size (min 0.6mm)) + (condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")) + +(rule "Board_1-hole to hole clearance (different nets)" + (constraint hole_to_hole (min 0.5mm)) + (condition "A.Net != B.Net")) + +(rule "Board_1-via to track clearance" + (constraint hole_clearance (min 0.254mm)) + (condition "A.Type == 'via' && B.Type == 'track'")) + +(rule "Board_1-via to via clearance (same nets)" + (constraint hole_to_hole (min 0.254mm)) + (condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net")) + +(rule "Board_1-pad to pad clearance (with hole, different nets)" + (constraint hole_to_hole (min 0.5mm)) + (condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net")) + +(rule "Board_1-pad to pad clearance (without hole, different nets)" + (constraint clearance (min 0.127mm)) + (condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net")) + +(rule "Board_1-NPTH to Track clearance)" + (constraint hole_clearance (min 0.254mm)) + (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'")) + +(rule "Board_1-PTH to Track clearance)" + (constraint hole_clearance (min 0.33mm)) + (condition "A.isPlated() && B.Type == 'track'")) + +(rule "Board_1-Pad to Track clearance)" + (constraint clearance (min 0.2mm)) + (condition "A.isPlated() && B.Type == 'track'")) diff --git a/boards/panels/explorer-both/.explorer-both.kicad_pcb b/boards/panels/explorer-both/.explorer-both.kicad_pcb new file mode 100644 index 0000000..c71e328 --- /dev/null +++ b/boards/panels/explorer-both/.explorer-both.kicad_pcb @@ -0,0 +1,13040 @@ +(kicad_pcb (version 20221018) (generator pcbnew) + + (general + (thickness 1.6) + ) + + (paper "A4") + (layers + (0 "F.Cu" signal) + (31 "B.Cu" signal) + (32 "B.Adhes" user "B.Adhesive") + (33 "F.Adhes" user "F.Adhesive") + (34 "B.Paste" user) + (35 "F.Paste" user) + (36 "B.SilkS" user "B.Silkscreen") + (37 "F.SilkS" user "F.Silkscreen") + (38 "B.Mask" user) + (39 "F.Mask" user) + (40 "Dwgs.User" user "User.Drawings") + (41 "Cmts.User" user "User.Comments") + (42 "Eco1.User" user "User.Eco1") + (43 "Eco2.User" user "User.Eco2") + (44 "Edge.Cuts" user) + (45 "Margin" user) + (46 "B.CrtYd" user "B.Courtyard") + (47 "F.CrtYd" user "F.Courtyard") + (48 "B.Fab" user) + (49 "F.Fab" user) + (50 "User.1" user) + (51 "User.2" user) + (52 "User.3" user) + (53 "User.4" user) + (54 "User.5" user) + (55 "User.6" user) + (56 "User.7" user) + (57 "User.8" user) + (58 "User.9" user) + ) + + (setup + (pad_to_mask_clearance 0) + (aux_axis_origin 124.436 20) + (grid_origin 124.436 20) + (pcbplotparams + (layerselection 0x00010fc_ffffffff) + (plot_on_all_layers_selection 0x0000000_00000000) + (disableapertmacros false) + (usegerberextensions false) + (usegerberattributes true) + (usegerberadvancedattributes true) + (creategerberjobfile true) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (dxfpolygonmode true) + (dxfimperialunits true) + (dxfusepcbnewfont true) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (sketchpadsonfab false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + + (net 0 "") + (net 1 "Board_0-/AUDIO_OUT") + (net 2 "Board_0-/AUDIO_OUT_FILTER") + (net 3 "Board_0-/DAC_OUT") + (net 4 "Board_0-/FILTER_OUT") + (net 5 "Board_0-/PROG") + (net 6 "Board_0-/PWR") + (net 7 "Board_0-GND") + (net 8 "Board_0-Net-(C1-Pad1)") + (net 9 "Board_0-Net-(C10-Pad1)") + (net 10 "Board_0-Net-(C5-Pad2)") + (net 11 "Board_0-Net-(IC2-+INPUT)") + (net 12 "Board_0-Net-(IC2-GAIN_1)") + (net 13 "Board_0-Net-(IC2-GAIN_2)") + (net 14 "Board_0-Net-(JPROG1-Pin_3)") + (net 15 "Board_0-VCC") + (net 16 "Board_0-unconnected-(IC1-PA1-Pad4)") + (net 17 "Board_0-unconnected-(IC1-PA2-Pad5)") + (net 18 "Board_0-unconnected-(IC1-PA3{slash}EXTCLK-Pad7)") + (net 19 "Board_0-unconnected-(IC1-PA7-Pad3)") + (net 20 "Board_0-unconnected-(IC2-BYPASS-Pad7)") + (net 21 "Board_1-GND") + (net 22 "Board_1-Net-(D1-K)") + (net 23 "Board_1-VCC") + + (footprint "NPTH" (layer "F.Cu") + (tstamp 009ece37-1744-4b60-9f94-01b7d4a6448e) + (at 164.5 62) + (attr through_hole) + (fp_text reference "KiKit_MB_10_4" (at 0 0.5) (layer "F.SilkS") hide + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 5030bafd-514e-4930-a9d9-89014bb1118b) + ) + (fp_text value "NPTH" (at 0 -0.5) (layer "F.Fab") hide + (effects (font (size 1 1) (thickness 0.15))) + (tstamp e7174517-daf3-4e5a-84e2-e6e8b647e9e7) + ) + (pad "" np_thru_hole circle (at 0 0) (size 0.5 0.5) (drill 0.5) (layers "*.Mask") (tstamp 4a44f268-b4ae-493d-9b9c-f53fbd2dd38c)) + ) + + (footprint "NPTH" (layer "F.Cu") + (tstamp 0254a1d9-3b0a-4849-a928-db43402cd3ea) + (at 146.833334 62) + (attr through_hole) + (fp_text reference "KiKit_MB_8_6" (at 0 0.5) (layer "F.SilkS") hide + (effects (font (size 1 1) (thickness 0.15))) + (tstamp b7233523-42a1-4e4f-888e-1817995aeeee) + ) + (fp_text value "NPTH" (at 0 -0.5) (layer "F.Fab") hide + (effects (font (size 1 1) (thickness 0.15))) + (tstamp b4e77b07-b483-4c29-b9c7-5b6f8fec19bf) + ) + (pad "" np_thru_hole circle (at 0 0) (size 0.5 0.5) (drill 0.5) (layers "*.Mask") (tstamp 75e46298-d51a-4c10-a2fb-ef910d5e6a08)) + ) + + (footprint "NPTH" (layer "F.Cu") + (tstamp 029a4f54-8c2b-4371-8c64-7c5ef517e7ab) + (at 166.209333 98.064) + (attr through_hole) + (fp_text reference "KiKit_MB_20_2" (at 0 0.5) (layer "F.SilkS") hide + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 1ca450e6-f891-4ec9-8e64-db20872a6fed) + ) + (fp_text value "NPTH" (at 0 -0.5) (layer "F.Fab") hide + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 223e0e61-5f17-4087-bb8e-900d8577660f) + ) + (pad "" np_thru_hole circle (at 0 0) (size 0.5 0.5) (drill 0.5) (layers "*.Mask") (tstamp 8a4f9ed9-8008-44df-84cd-150d170dafd7)) + ) + + (footprint "NPTH" (layer "F.Cu") + (tstamp 02b7fd98-98c4-4ce8-8473-8a4e58e96a12) + (at 150.166666 62) + (attr through_hole) + (fp_text reference "KiKit_MB_8_2" (at 0 0.5) (layer "F.SilkS") hide + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 3ddda348-3130-4ca1-9a39-be693bb4a95e) + ) + (fp_text value "NPTH" (at 0 -0.5) (layer "F.Fab") hide + (effects (font (size 1 1) (thickness 0.15))) + (tstamp d80d9103-d31f-4b50-92ab-c59826c57de9) + ) + (pad "" np_thru_hole circle (at 0 0) (size 0.5 0.5) (drill 0.5) (layers "*.Mask") (tstamp b759de2d-e6c3-41ff-bdbf-d91c7e7869ca)) + ) + + (footprint "NPTH" (layer "F.Cu") + (tstamp 02f046f4-a977-4916-8572-3c8c56d88446) + (at 146 64.936) + (attr through_hole) + (fp_text reference "KiKit_MB_13_1" (at 0 0.5) (layer "F.SilkS") hide + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 0583e1eb-c650-4cb3-a419-255ae69c9410) + ) + (fp_text value "NPTH" (at 0 -0.5) (layer "F.Fab") hide + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 35318447-c0ab-417d-9448-283dd7981df6) + ) + (pad "" np_thru_hole circle (at 0 0) (size 0.5 0.5) (drill 0.5) (layers "*.Mask") (tstamp d9ed9eda-d72a-4c6d-b074-b3b06bc0377c)) + ) + + (footprint "NPTH" (layer "F.Cu") + (tstamp 04cfe96f-8153-403e-a325-c0fbf83d7dbd) + (at 131.666667 64.936) + (attr through_hole) + (fp_text reference "KiKit_MB_11_3" (at 0 0.5) (layer "F.SilkS") hide + (effects (font (size 1 1) (thickness 0.15))) + (tstamp fba75ba6-72dd-4d5a-87a1-7ca424110ddf) + ) + (fp_text value "NPTH" (at 0 -0.5) (layer "F.Fab") hide + (effects (font (size 1 1) (thickness 0.15))) + (tstamp da7883b7-2549-437e-abe9-18ca49bb5267) + ) + (pad "" np_thru_hole circle (at 0 0) (size 0.5 0.5) (drill 0.5) (layers "*.Mask") (tstamp d081c124-fca2-45f0-8a77-efae8f787207)) + ) + + (footprint "NPTH" (layer "F.Cu") + (tstamp 05f5fdc3-e84f-4dcd-ab73-c55d26b17e63) + (at 148.5 62) + (attr through_hole) + (fp_text reference "KiKit_MB_8_4" (at 0 0.5) (layer "F.SilkS") hide + (effects (font (size 1 1) (thickness 0.15))) + (tstamp c541a9fa-00ef-422f-b0e2-e6c562d435fb) + ) + (fp_text value "NPTH" (at 0 -0.5) (layer "F.Fab") hide + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 8063af8d-9fa8-4cd2-9805-63217b2584fa) + ) + (pad "" np_thru_hole circle (at 0 0) (size 0.5 0.5) (drill 0.5) (layers "*.Mask") (tstamp 96b57fff-9544-4c78-8f4f-058a5fc603bf)) + ) + + (footprint "Capacitor_SMD:C_0805_2012Metric_Pad1.18x1.45mm_HandSolder" (layer "F.Cu") + (tstamp 07b21166-c858-4bee-978f-59e529da4bb4) + (at 154.9 44.6875 90) + (descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf, https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator") + (tags "capacitor handsolder") + (property "Sheetfile" "explorer.kicad_sch") + (property "Sheetname" "") + (property "ki_description" "Unpolarized capacitor") + (property "ki_keywords" "cap capacitor") + (path "/aba54dd4-494c-4308-b1f9-ceb2744fe5fe") + (attr smd) + (fp_text reference "Board_0-C3" (at -2.6 0 unlocked) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp efe44b5d-febe-4644-a276-fea9f30407a0) + ) + (fp_text value "10uF" (at 0 1.68 90 unlocked) (layer "F.Fab") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 0bdcffc4-8105-49dc-b082-23523689cb14) + ) + (fp_text user "${REFERENCE}" (at 0 0 90 unlocked) (layer "F.Fab") + (effects (font (size 0.5 0.5) (thickness 0.08))) + (tstamp 3c2578d9-2fc6-4cd2-8272-aa480586d5fb) + ) + (fp_line (start -0.261252 -0.735) (end 0.261252 -0.735) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 8206faa4-392f-4b30-ac2b-33ad674df0f3)) + (fp_line (start -0.261252 0.735) (end 0.261252 0.735) + (stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp ab0bbfbc-e4ea-49ae-abd6-9c4bd5044073)) + (fp_line (start -1.88 -0.98) (end 1.88 -0.98) + (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 828f2d30-fac5-451f-b999-e3f6093b23e5)) + (fp_line (start -1.88 0.98) (end -1.88 -0.98) + (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 37aee953-4013-495d-907b-2d0d3f5deec6)) + (fp_line (start 1.88 -0.98) (end 1.88 0.98) + (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 400d414b-4430-4b7b-aa4e-ab1e186f1705)) + (fp_line (start 1.88 0.98) (end -1.88 0.98) + (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp b197e3ef-c323-4c5d-8d2a-f28fab453f5e)) + (fp_line (start -1 -0.625) (end 1 -0.625) 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"keep_text_aligned": true, + "suppress_zeroes": false, + "text_position": 0, + "units_format": 1 + }, + "fab_line_width": 0.09999999999999999, + "fab_text_italic": false, + "fab_text_size_h": 1.0, + "fab_text_size_v": 1.0, + "fab_text_thickness": 0.15, + "fab_text_upright": false, + "other_line_width": 0.15, + "other_text_italic": false, + "other_text_size_h": 1.0, + "other_text_size_v": 1.0, + "other_text_thickness": 0.15, + "other_text_upright": false, + "pads": { + "drill": 0.762, + "height": 1.524, + "width": 1.524 + }, + "silk_line_width": 0.15, + "silk_text_italic": false, + "silk_text_size_h": 1.0, + "silk_text_size_v": 1.0, + "silk_text_thickness": 0.15, + "silk_text_upright": false, + "zones": { + "min_clearance": 0.5 + } + }, + "diff_pair_dimensions": [ + { + "gap": 0.0, + "via_gap": 0.0, + "width": 0.0 + } + ], + "drc_exclusions": [], + "meta": { + "version": 2 + }, + "rule_severities": { + "annular_width": "error", + "clearance": "error", + "connection_width": "warning", + "copper_edge_clearance": "error", + "copper_sliver": "warning", + "courtyards_overlap": "error", + "diff_pair_gap_out_of_range": "error", + "diff_pair_uncoupled_length_too_long": "error", + "drill_out_of_range": "error", + "duplicate_footprints": "warning", + "extra_footprint": "warning", + "footprint": "error", + "footprint_type_mismatch": "ignore", + "hole_clearance": "error", + "hole_near_hole": "error", + "invalid_outline": "error", + "isolated_copper": "warning", + "item_on_disabled_layer": "error", + "items_not_allowed": "error", + "length_out_of_range": "error", + "lib_footprint_issues": "warning", + "lib_footprint_mismatch": "warning", + "malformed_courtyard": "error", + "microvia_drill_out_of_range": "error", + "missing_courtyard": "ignore", + "missing_footprint": "warning", + "net_conflict": "warning", + "npth_inside_courtyard": "ignore", + "padstack": "warning", + "pth_inside_courtyard": "ignore", + "shorting_items": "error", + "silk_edge_clearance": "warning", + "silk_over_copper": "warning", + "silk_overlap": "warning", + "skew_out_of_range": "error", + "solder_mask_bridge": "error", + "starved_thermal": "error", + "text_height": "warning", + "text_thickness": "warning", + "through_hole_pad_without_hole": "error", + "too_many_vias": "error", + "track_dangling": "warning", + "track_width": "error", + "tracks_crossing": "error", + "unconnected_items": "error", + "unresolved_variable": "error", + "via_dangling": "warning", + "zones_intersect": "error" + }, + "rules": { + "max_error": 0.005, + "min_clearance": 0.0, + "min_connection": 0.0, + "min_copper_edge_clearance": 0.0, + "min_hole_clearance": 0.25, + "min_hole_to_hole": 0.25, + "min_microvia_diameter": 0.19999999999999998, + "min_microvia_drill": 0.09999999999999999, + "min_resolved_spokes": 2, + "min_silk_clearance": 0.0, + "min_text_height": 0.7999999999999999, + "min_text_thickness": 0.08, + "min_through_hole_diameter": 0.3, + "min_track_width": 0.0, + "min_via_annular_width": 0.09999999999999999, + "min_via_diameter": 0.5, + "solder_mask_clearance": 0.0, + "solder_mask_min_width": 0.0, + "solder_mask_to_copper_clearance": 0.0, + "use_height_for_length_calcs": true + }, + "teardrop_options": [ + { + "td_allow_use_two_tracks": false, + "td_curve_segcount": 5, + "td_on_pad_in_zone": false, + "td_onpadsmd": false, + "td_onroundshapesonly": false, + "td_ontrackend": true, + "td_onviapad": false + } + ], + "teardrop_parameters": [ + { + "td_curve_segcount": 5, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_target_name": "td_round_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_curve_segcount": 5, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_target_name": "td_rect_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_curve_segcount": 5, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 3.0, + "td_maxlen": 1.0, + "td_target_name": "td_track_end", + "td_width_to_size_filter_ratio": 0.9 + } + ], + "track_widths": [ + 0.0, + 0.2, + 0.3, + 0.4, + 0.8 + ], + "via_dimensions": [ + { + "diameter": 0.0, + "drill": 0.0 + } + ], + "zones_allow_external_fillets": false + }, + "layer_presets": [], + "viewports": [] + }, + "boards": [], + "cvpcb": { + "equivalence_files": [] + }, + "libraries": { + "pinned_footprint_libs": [], + "pinned_symbol_libs": [] + }, + "meta": { + "filename": ".explorer-both.kicad_pro", + "version": 1 + }, + "net_settings": { + "classes": [ + { + "bus_width": 12, + "clearance": 0.2, + "diff_pair_gap": 0.25, + "diff_pair_via_gap": 0.25, + "diff_pair_width": 0.2, + "line_style": 0, + "microvia_diameter": 0.3, + "microvia_drill": 0.1, + "name": "Default", + "pcb_color": "rgba(0, 0, 0, 0.000)", + "schematic_color": "rgba(0, 0, 0, 0.000)", + "track_width": 0.35, + "via_diameter": 0.8, + "via_drill": 0.4, + "wire_width": 6 + }, + { + "bus_width": 12, + "clearance": 0.2, + "diff_pair_gap": 0.25, + "diff_pair_via_gap": 0.25, + "diff_pair_width": 0.2, + "line_style": 0, + "microvia_diameter": 0.3, + "microvia_drill": 0.1, + "name": "power", + "pcb_color": "rgba(0, 0, 0, 0.000)", + "schematic_color": "rgba(0, 0, 0, 0.000)", + "track_width": 1.0, + "via_diameter": 0.8, + "via_drill": 0.4, + "wire_width": 6 + }, + { + "bus_width": 12, + "clearance": 0.2, + "diff_pair_gap": 0.25, + "diff_pair_via_gap": 0.25, + "diff_pair_width": 0.2, + "line_style": 0, + "microvia_diameter": 0.3, + "microvia_drill": 0.1, + "name": "Board_0-Default", + "pcb_color": "rgba(0, 0, 0, 0.000)", + "schematic_color": "rgba(0, 0, 0, 0.000)", + "track_width": 0.35, + "via_diameter": 0.8, + "via_drill": 0.4, + "wire_width": 6 + }, + { + "bus_width": 12, + "clearance": 0.2, + "diff_pair_gap": 0.25, + "diff_pair_via_gap": 0.25, + "diff_pair_width": 0.2, + "line_style": 0, + "microvia_diameter": 0.3, + "microvia_drill": 0.1, + "name": "Board_0-power", + "pcb_color": "rgba(0, 0, 0, 0.000)", + "schematic_color": "rgba(0, 0, 0, 0.000)", + "track_width": 1.0, + "via_diameter": 0.8, + "via_drill": 0.4, + "wire_width": 6 + }, + { + "bus_width": 12, + "clearance": 0.2, + "diff_pair_gap": 0.25, + "diff_pair_via_gap": 0.25, + "diff_pair_width": 0.2, + "line_style": 0, + "microvia_diameter": 0.3, + "microvia_drill": 0.1, + "name": "Board_1-Default", + "pcb_color": "rgba(0, 0, 0, 0.000)", + "schematic_color": "rgba(0, 0, 0, 0.000)", + "track_width": 1.0, + "via_diameter": 0.8, + "via_drill": 0.4, + "wire_width": 6 + } + ], + "meta": { + "version": 3 + }, + "net_colors": null, + "netclass_assignments": null, + "netclass_patterns": [ + { + "netclass": "Board_0-Default", + "pattern": "Board_0-/DAC_OUT" + }, + { + "netclass": "Board_0-Default", + "pattern": "Board_0-Net-(IC2-+INPUT)" + }, + { + "netclass": "Board_0-Default", + "pattern": "Board_0-unconnected-(IC1-PA3{slash}EXTCLK-Pad7)" + }, + { + "netclass": "Board_0-Default", + "pattern": "Board_0-Net-(IC2-GAIN_2)" + }, + { + "netclass": "Board_0-Default", + "pattern": "Board_0-Net-(C10-Pad1)" + }, + { + "netclass": "Board_0-Default", + "pattern": "Board_0-unconnected-(IC1-PA2-Pad5)" + }, + { + "netclass": "Board_0-Default", + "pattern": "Board_0-/FILTER_OUT" + }, + { + "netclass": "Board_0-Default", + "pattern": "Board_0-Net-(IC2-GAIN_1)" + }, + { + "netclass": "Board_0-Default", + "pattern": "Board_0-unconnected-(IC2-BYPASS-Pad7)" + }, + { + "netclass": "Board_0-Default", + "pattern": "Board_0-Net-(JPROG1-Pin_3)" + }, + { + "netclass": "Board_0-Default", + "pattern": "Board_0-Net-(C5-Pad2)" + }, + { + "netclass": "Board_0-Default", + "pattern": "Board_0-unconnected-(IC1-PA1-Pad4)" + }, + { + "netclass": "Board_0-Default", + "pattern": "Board_0-unconnected-(IC1-PA7-Pad3)" + }, + { + "netclass": "Board_0-Default", + "pattern": "Board_0-/PROG" + }, + { + "netclass": "Board_0-Default", + "pattern": "Board_0-Net-(C1-Pad1)" + }, + { + "netclass": "Board_0-power", + "pattern": "Board_0-VCC" + }, + { + "netclass": "Board_0-power", + "pattern": "Board_0-GND" + }, + { + "netclass": "Board_0-power", + "pattern": "Board_0-/PWR" + }, + { + "netclass": "Board_0-power", + "pattern": "Board_0-/AUDIO_OUT*" + }, + { + "netclass": "Board_1-Default", + "pattern": "Board_1-Net-(D1-K)" + }, + { + "netclass": "Board_1-Default", + "pattern": "Board_1-VCC" + }, + { + "netclass": "Board_1-Default", + "pattern": "Board_1-GND" + } + ] + }, + "pcbnew": { + "last_paths": { + "gencad": "", + "idf": "", + "netlist": "", + "specctra_dsn": "", + "step": "", + "vrml": "" + }, + "page_layout_descr_file": "" + }, + "schematic": { + "legacy_lib_dir": "", + "legacy_lib_list": [] + }, + "sheets": [], + "text_variables": {} +} \ No newline at end of file diff --git a/boards/panels/explorer-both/explorer-both.kicad_dru b/boards/panels/explorer-both/explorer-both.kicad_dru new file mode 100644 index 0000000..8c52961 --- /dev/null +++ b/boards/panels/explorer-both/explorer-both.kicad_dru @@ -0,0 +1,178 @@ +(version 1) + +(rule "Board_0-Minimum Trace Width (outer layer)" + (constraint track_width (min 5mil)) + (layer outer) + (condition "A.Type == 'track'")) + +(rule "Board_0-Minimum Trace Spacing (outer layer)" + (constraint clearance (min 5mil)) + (layer outer) + (condition "A.Type == 'track' && B.Type == A.Type")) + +(rule "Board_0-Minimum Trace Width and Spacing (inner layer)" + (constraint track_width (min 3.5mil)) + (layer inner) + (condition "A.Type == 'track'")) + +(rule "Board_0-Minimum Trace Spacing (inner layer)" + (constraint clearance (min 3.5mil)) + (layer inner) + (condition "A.Type == 'track' && B.Type == A.Type")) + +(rule "Board_0-Minimum Text" + (constraint text_thickness (min 0.15mm)) + (constraint text_height (min 1mm)) + (layer "?.Silkscreen")) + +(rule "Board_0-Pad to Silkscreen" + (constraint silk_clearance (min 0.15mm)) + (layer outer) + (condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')")) + +(rule "Board_0-Trace to Outline" + (constraint edge_clearance (min 0.3mm)) + (condition "A.Type == 'track'")) + +(rule "Board_0-drill hole size (mechanical)" + (constraint hole_size (min 0.2mm) (max 6.3mm))) + +(rule "Board_0-Minimum Via Hole Size" + (constraint hole_size (min 0.2mm)) + (condition "A.Type == 'via'")) + +(rule "Board_0-Minimum Via Diameter" + (constraint via_diameter (min 0.45mm)) + (condition "A.Type == 'via'")) + +(rule "Board_0-PTH Hole Size" + (constraint hole_size (min 0.2mm) (max 6.35mm)) + (condition "A.isPlated()")) + +(rule "Board_0-Minimum Non-plated Hole Size" + (constraint hole_size (min 0.5mm)) + (condition "A.Type == 'pad' && !A.isPlated()")) + +(rule "Board_0-Minimum Castellated Hole Size" + (constraint hole_size (min 0.6mm)) + (condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")) + +(rule "Board_0-hole to hole clearance (different nets)" + (constraint hole_to_hole (min 0.5mm)) + (condition "A.Net != B.Net")) + +(rule "Board_0-via to track clearance" + (constraint hole_clearance (min 0.254mm)) + (condition "A.Type == 'via' && B.Type == 'track'")) + +(rule "Board_0-via to via clearance (same nets)" + (constraint hole_to_hole (min 0.254mm)) + (condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net")) + +(rule "Board_0-pad to pad clearance (with hole, different nets)" + (constraint hole_to_hole (min 0.5mm)) + (condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net")) + +(rule "Board_0-pad to pad clearance (without hole, different nets)" + (constraint clearance (min 0.127mm)) + (condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net")) + +(rule "Board_0-NPTH to Track clearance)" + (constraint hole_clearance (min 0.254mm)) + (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'")) + +(rule "Board_0-PTH to Track clearance)" + (constraint hole_clearance (min 0.33mm)) + (condition "A.isPlated() && B.Type == 'track'")) + +(rule "Board_0-Pad to Track clearance)" + (constraint clearance (min 0.2mm)) + (condition "A.isPlated() && B.Type == 'track'")) +(rule "Board_1-Minimum Trace Width (outer layer)" + (constraint track_width (min 5mil)) + (layer outer) + (condition "A.Type == 'track'")) + +(rule "Board_1-Minimum Trace Spacing (outer layer)" + (constraint clearance (min 5mil)) + (layer outer) + (condition "A.Type == 'track' && B.Type == A.Type")) + +(rule "Board_1-Minimum Trace Width and Spacing (inner layer)" + (constraint track_width (min 3.5mil)) + (layer inner) + (condition "A.Type == 'track'")) + +(rule "Board_1-Minimum Trace Spacing (inner layer)" + (constraint clearance (min 3.5mil)) + (layer inner) + (condition "A.Type == 'track' && B.Type == A.Type")) + +(rule "Board_1-Minimum Text" + (constraint text_thickness (min 0.15mm)) + (constraint text_height (min 1mm)) + (layer "?.Silkscreen")) + +(rule "Board_1-Pad to Silkscreen" + (constraint silk_clearance (min 0.15mm)) + (layer outer) + (condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')")) + +(rule "Board_1-Trace to Outline" + (constraint edge_clearance (min 0.3mm)) + (condition "A.Type == 'track'")) + +(rule "Board_1-drill hole size (mechanical)" + (constraint hole_size (min 0.2mm) (max 6.3mm))) + +(rule "Board_1-Minimum Via Hole Size" + (constraint hole_size (min 0.2mm)) + (condition "A.Type == 'via'")) + +(rule "Board_1-Minimum Via Diameter" + (constraint via_diameter (min 0.45mm)) + (condition "A.Type == 'via'")) + +(rule "Board_1-PTH Hole Size" + (constraint hole_size (min 0.2mm) (max 6.35mm)) + (condition "A.isPlated()")) + +(rule "Board_1-Minimum Non-plated Hole Size" + (constraint hole_size (min 0.5mm)) + (condition "A.Type == 'pad' && !A.isPlated()")) + +(rule "Board_1-Minimum Castellated Hole Size" + (constraint hole_size (min 0.6mm)) + (condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")) + +(rule "Board_1-hole to hole clearance (different nets)" + (constraint hole_to_hole (min 0.5mm)) + (condition "A.Net != B.Net")) + +(rule "Board_1-via to track clearance" + (constraint hole_clearance (min 0.254mm)) + (condition "A.Type == 'via' && B.Type == 'track'")) + +(rule "Board_1-via to via clearance (same nets)" + (constraint hole_to_hole (min 0.254mm)) + (condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net")) + +(rule "Board_1-pad to pad clearance (with hole, different nets)" + (constraint hole_to_hole (min 0.5mm)) + (condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net")) + +(rule "Board_1-pad to pad clearance (without hole, different nets)" + (constraint clearance (min 0.127mm)) + (condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net")) + +(rule "Board_1-NPTH to Track clearance)" + (constraint hole_clearance (min 0.254mm)) + (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'")) + +(rule "Board_1-PTH to Track clearance)" + (constraint hole_clearance (min 0.33mm)) + (condition "A.isPlated() && B.Type == 'track'")) + +(rule "Board_1-Pad to Track clearance)" + (constraint clearance (min 0.2mm)) + (condition "A.isPlated() && B.Type == 'track'")) diff --git a/boards/panels/explorer-both/explorer-both.kicad_pcb b/boards/panels/explorer-both/explorer-both.kicad_pcb new file mode 100644 index 0000000..f25e30b --- /dev/null +++ b/boards/panels/explorer-both/explorer-both.kicad_pcb @@ -0,0 +1,11900 @@ +(kicad_pcb (version 20221018) (generator pcbnew) + + (general + (thickness 1.6) + ) + + (paper "A4") + (layers + (0 "F.Cu" signal) + (31 "B.Cu" signal) + (32 "B.Adhes" user "B.Adhesive") + (33 "F.Adhes" user "F.Adhesive") + (34 "B.Paste" user) + (35 "F.Paste" user) + (36 "B.SilkS" user "B.Silkscreen") + (37 "F.SilkS" user "F.Silkscreen") + (38 "B.Mask" user) + (39 "F.Mask" user) + (40 "Dwgs.User" user "User.Drawings") + (41 "Cmts.User" user "User.Comments") + (42 "Eco1.User" user "User.Eco1") + (43 "Eco2.User" user "User.Eco2") + (44 "Edge.Cuts" user) + (45 "Margin" user) + (46 "B.CrtYd" user "B.Courtyard") + (47 "F.CrtYd" user "F.Courtyard") + (48 "B.Fab" user) + (49 "F.Fab" user) + (50 "User.1" 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"error", + "length_out_of_range": "error", + "lib_footprint_issues": "warning", + "lib_footprint_mismatch": "warning", + "malformed_courtyard": "error", + "microvia_drill_out_of_range": "error", + "missing_courtyard": "ignore", + "missing_footprint": "warning", + "net_conflict": "warning", + "npth_inside_courtyard": "ignore", + "padstack": "warning", + "pth_inside_courtyard": "ignore", + "shorting_items": "error", + "silk_edge_clearance": "warning", + "silk_over_copper": "warning", + "silk_overlap": "warning", + "skew_out_of_range": "error", + "solder_mask_bridge": "error", + "starved_thermal": "error", + "text_height": "warning", + "text_thickness": "warning", + "through_hole_pad_without_hole": "error", + "too_many_vias": "error", + "track_dangling": "warning", + "track_width": "error", + "tracks_crossing": "error", + "unconnected_items": "error", + "unresolved_variable": "error", + "via_dangling": "warning", + "zones_intersect": "error" + }, + "rules": { + "max_error": 0.005, + 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"pattern": "Board_0-Net-(IC2-GAIN_1)" + }, + { + "netclass": "Board_0-Default", + "pattern": "Board_0-Net-(IC2-GAIN_2)" + }, + { + "netclass": "Board_0-Default", + "pattern": "Board_0-Net-(JPROG1-Pin_3)" + }, + { + "netclass": "Board_0-Default", + "pattern": "Board_0-/FILTER_OUT" + }, + { + "netclass": "Board_0-Default", + "pattern": "Board_0-Net-(C10-Pad1)" + }, + { + "netclass": "Board_0-power", + "pattern": "Board_0-VCC" + }, + { + "netclass": "Board_0-power", + "pattern": "Board_0-GND" + }, + { + "netclass": "Board_0-power", + "pattern": "Board_0-/PWR" + }, + { + "netclass": "Board_0-power", + "pattern": "Board_0-/AUDIO_OUT*" + }, + { + "netclass": "Board_1-Default", + "pattern": "Board_1-Net-(D1-K)" + }, + { + "netclass": "Board_1-Default", + "pattern": "Board_1-GND" + }, + { + "netclass": "Board_1-Default", + "pattern": "Board_1-VCC" + } + ] + }, + "pcbnew": { + "last_paths": { + "gencad": "", + "idf": "", + "netlist": "", + "specctra_dsn": "", + "step": "", + "vrml": "" + }, + "page_layout_descr_file": "" + }, + "schematic": { + "legacy_lib_dir": "", + "legacy_lib_list": [] + }, + "sheets": [], + "text_variables": {} +} diff --git a/boards/panels/explorer-both/jlcpcb/project.db b/boards/panels/explorer-both/jlcpcb/project.db new file mode 100644 index 0000000..5fb5447 Binary files /dev/null and b/boards/panels/explorer-both/jlcpcb/project.db differ diff --git a/boards/panels/explorer-both/panelize_multiple.py b/boards/panels/explorer-both/panelize_multiple.py new file mode 100644 index 0000000..4e849a5 --- /dev/null +++ b/boards/panels/explorer-both/panelize_multiple.py @@ -0,0 +1,114 @@ +from kikit import panelize_ui_impl as ki +from kikit.units import mm, deg +from kikit.panelize import Panel, BasicGridPosition, Origin +from pcbnewTransition.pcbnew import LoadBoard, VECTOR2I +from pcbnewTransition import pcbnew +from itertools import chain + + + +############### Custom config +board1_path = "../explorer/explorer.kicad_pcb" +board2_path = "../explorer-light/explorer-light.kicad_pcb" +output_path = "./explorer-both.kicad_pcb" + +board_spacing = 3*mm + +################ KiKit Panel Config (Only deviations from default) + +framing={ + "type": "none" #only rail on top and bottom +} + +cuts = { + "type": "mousebites" + } +tabs = { #Add tabs between board and board as well as board and rail + "type":"spacing", #Place them with constant width and spacing + "vwidth": "5mm", + "spacing" : "5mm" + } +tooling = { + "type": "none" + } + +# Obtain full config by combining above with default +preset = ki.obtainPreset([], tabs=tabs, cuts=cuts, framing=framing, tooling=tooling) + + + +################ Adjusted `panelize_ui#doPanelization` + +# Prepare +board1 = LoadBoard(board1_path) +board2 = LoadBoard(board2_path) +panel = Panel(output_path) + + +panel.inheritDesignSettings(board1) +panel.inheritProperties(board1) +panel.inheritTitleBlock(board1) + + + + +###### Manually build layout. Inspired by `panelize_ui_impl#buildLayout` +sourceArea1 = ki.readSourceArea(preset["source"], board1) +sourceArea2 = ki.readSourceArea(preset["source"], board2) + +substrateCount = len(panel.substrates) # Store number of previous boards (probably 0) +# Prepare renaming nets and references +netRenamer = lambda x, y: "Board_{n}-{orig}".format(n=x, orig=y) +#refRenamer = lambda x, y: "Board_{n}-{orig}".format(n=x, orig=y) +refRenamer = lambda x, y: x*"_" + "{orig}".format(n=x, orig=y) +# I want to mantain the silkscreen as in original. I will prepend n zero-width joiner +# characters to mantain the appearances but give them different names +#netRenamer = lambda x, y: x*b"".decode("utf-8") + "{orig}".format(n=x, orig=y) +#refRenamer = lambda x, y: x*b"".decode("utf-8") + "{orig}".format(n=x, orig=y) + +# Actually place the individual boards +# Use existing grid positioner +# Place two boards above each other +panelOrigin = VECTOR2I(0,0) +placer = BasicGridPosition(board_spacing, board_spacing) #HorSpace, VerSpace +area1 = panel.appendBoard(board1_path, panelOrigin + placer.position(0,0, None) , origin=Origin.Center, sourceArea=sourceArea1, netRenamer=netRenamer, refRenamer=refRenamer) +area2 = panel.appendBoard(board2_path, panelOrigin + placer.position(1,0, area1), origin=Origin.Center, sourceArea=sourceArea2, netRenamer=netRenamer, refRenamer=refRenamer, inheritDrc=False) + + +substrates = panel.substrates[substrateCount:] # Collect set of newly added boards + +# Prepare frame and partition +framingSubstrates = ki.dummyFramingSubstrate(substrates, preset) +panel.buildPartitionLineFromBB(framingSubstrates) +backboneCuts = ki.buildBackBone(preset["layout"], panel, substrates, preset) + + +######## --------------------- Continue doPanelization + +tabCuts = ki.buildTabs(preset, panel, substrates, framingSubstrates) + +frameCuts = ki.buildFraming(preset, panel) + + +ki.buildTooling(preset, panel) +ki.buildFiducials(preset, panel) +for textSection in ["text", "text2", "text3", "text4"]: + ki.buildText(preset[textSection], panel) +ki.buildPostprocessing(preset["post"], panel) + +ki.makeTabCuts(preset, panel, tabCuts) +ki.makeOtherCuts(preset, panel, chain(backboneCuts, frameCuts)) + + +ki.buildCopperfill(preset["copperfill"], panel) + +ki.setStackup(preset["source"], panel) +ki.setPageSize(preset["page"], panel, board1) +ki.positionPanel(preset["page"], panel) + +ki.runUserScript(preset["post"], panel) + +ki.buildDebugAnnotation(preset["debug"], panel) + +panel.save(reconstructArcs=preset["post"]["reconstructarcs"], + refillAllZones=preset["post"]["refillzones"]) diff --git a/boards/panels/explorer-panel/Production/explorer-panel_panelized.kicad_pcb b/boards/panels/explorer-panel/Production/explorer-panel_panelized.kicad_pcb new file mode 100644 index 0000000..af546a9 --- /dev/null +++ b/boards/panels/explorer-panel/Production/explorer-panel_panelized.kicad_pcb @@ -0,0 +1,25022 @@ +(kicad_pcb (version 20221018) (generator pcbnew) + + (general + (thickness 1.6) + ) + + (paper "A4") + (layers + (0 "F.Cu" signal) + (31 "B.Cu" signal) + (32 "B.Adhes" user "B.Adhesive") + (33 "F.Adhes" user "F.Adhesive") + (34 "B.Paste" user) + (35 "F.Paste" user) + (36 "B.SilkS" user "B.Silkscreen") + (37 "F.SilkS" user "F.Silkscreen") + (38 "B.Mask" user) + (39 "F.Mask" user) + (40 "Dwgs.User" user "User.Drawings") + (41 "Cmts.User" user "User.Comments") + (42 "Eco1.User" user "User.Eco1") + (43 "Eco2.User" user "User.Eco2") + (44 "Edge.Cuts" user) + (45 "Margin" user) + (46 "B.CrtYd" user "B.Courtyard") + (47 "F.CrtYd" user "F.Courtyard") + (48 "B.Fab" user) + (49 "F.Fab" user) + (50 "User.1" user) + (51 "User.2" user) + (52 "User.3" user) + (53 "User.4" user) + (54 "User.5" user) + (55 "User.6" user) + (56 "User.7" user) + (57 "User.8" user) + (58 "User.9" user) + ) + + (setup + (pad_to_mask_clearance 0) + (aux_axis_origin 98.872 20) + (grid_origin 98.872 20) + (pcbplotparams + (layerselection 0x00010fc_ffffffff) + (plot_on_all_layers_selection 0x0000000_00000000) + (disableapertmacros false) + (usegerberextensions false) + (usegerberattributes true) + (usegerberadvancedattributes true) + (creategerberjobfile true) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (dxfpolygonmode true) + (dxfimperialunits true) + (dxfusepcbnewfont true) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (sketchpadsonfab false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + + (net 0 "") + (net 1 "Board_0-Board_0-/AUDIO_OUT") + (net 2 "Board_0-Board_0-/AUDIO_OUT_FILTER") + (net 3 "Board_0-Board_0-/DAC_OUT") + (net 4 "Board_0-Board_0-/FILTER_OUT") + (net 5 "Board_0-Board_0-/PROG") + (net 6 "Board_0-Board_0-/PWR") + (net 7 "Board_0-Board_0-GND") + (net 8 "Board_0-Board_0-Net-(C1-Pad1)") + (net 9 "Board_0-Board_0-Net-(C10-Pad1)") + (net 10 "Board_0-Board_0-Net-(C5-Pad2)") + (net 11 "Board_0-Board_0-Net-(IC2-+INPUT)") + (net 12 "Board_0-Board_0-Net-(IC2-GAIN_1)") + (net 13 "Board_0-Board_0-Net-(IC2-GAIN_2)") + (net 14 "Board_0-Board_0-Net-(JPROG1-Pin_3)") + (net 15 "Board_0-Board_0-VCC") + (net 16 "Board_0-Board_0-unconnected-(IC1-PA1-Pad4)") + (net 17 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a/boards/panels/explorer-panel/Production/jlcpcb/project.db b/boards/panels/explorer-panel/Production/jlcpcb/project.db new file mode 100644 index 0000000..894462c Binary files /dev/null and b/boards/panels/explorer-panel/Production/jlcpcb/project.db differ diff --git a/boards/panels/explorer-panel/Production/ordering_instructions.txt b/boards/panels/explorer-panel/Production/ordering_instructions.txt new file mode 100644 index 0000000..6662e38 --- /dev/null +++ b/boards/panels/explorer-panel/Production/ordering_instructions.txt @@ -0,0 +1,9 @@ +Ordering Instructions: +Panel dimensions: 98.26 x 136.63 mm. +Solder Mask: Red (Default) +Silkscreen: White (Default) +Layers: 2 +Finish: HASL Lead-free (Default) +Thickness: 1.6mm (Default) +Copper weight: 1oz (Default) +Minimum track width: 0.30mm (11.81mil) diff --git a/boards/panels/explorer-panel/Production/panel_config.json b/boards/panels/explorer-panel/Production/panel_config.json new file mode 100644 index 0000000..e52b32a --- /dev/null +++ b/boards/panels/explorer-panel/Production/panel_config.json @@ -0,0 +1,15 @@ +{ + "dimensionsInchesBtn": true, + "dimensionsMmBtn": false, + "panelSizeSmallerBtn": true, + "panelSizeLargerBtn": false, + "panelSizeXCtrl": "5.5", + "panelSizeYCtrl": "7.5", + "gapsVerticalCtrl": "0.0", + "gapsHorizontalCtrl": "0.0", + "removeRightVerticalCheck": false, + "productionBordersCheck": false, + "productionFiducialsCheck": false, + "productionExposeCheck": false, + "vScoreLayer": "User.Comments" +} \ No newline at end of file diff --git a/boards/panels/explorer-panel/Production/panelizer.log b/boards/panels/explorer-panel/Production/panelizer.log new file mode 100644 index 0000000..52ae9e8 --- /dev/null +++ b/boards/panels/explorer-panel/Production/panelizer.log @@ -0,0 +1,8 @@ +2024-03-02 21:58:01,642 - panelizer_logger - WARNING - +START: 2024-03-02T21:57:57.962560 + +Board: /home/emamaker/work/fmd/romecup2024/explorer-panel/Production/explorer-panel_panelized.kicad_pcb +Board dimensions: 98.26 x 68.06 mm. +You can fit 1 x 2 boards on the panel. +Ordering Instructions not found! No futher ordering warnings will be given. + diff --git a/boards/panels/explorer-panel/explorer-panel.kicad_pcb b/boards/panels/explorer-panel/explorer-panel.kicad_pcb new file mode 100644 index 0000000..e6758fa --- /dev/null +++ b/boards/panels/explorer-panel/explorer-panel.kicad_pcb @@ -0,0 +1,30186 @@ +(kicad_pcb (version 20221018) (generator pcbnew) + + (general + (thickness 1.6) + ) + + (paper "A4") + (layers + (0 "F.Cu" signal) + (31 "B.Cu" signal) + (32 "B.Adhes" user "B.Adhesive") + (33 "F.Adhes" user "F.Adhesive") + (34 "B.Paste" user) + (35 "F.Paste" user) + (36 "B.SilkS" user "B.Silkscreen") + (37 "F.SilkS" user "F.Silkscreen") + (38 "B.Mask" user) + (39 "F.Mask" user) + (40 "Dwgs.User" user "User.Drawings") + (41 "Cmts.User" user "User.Comments") + (42 "Eco1.User" user "User.Eco1") + (43 "Eco2.User" user "User.Eco2") + (44 "Edge.Cuts" user) + (45 "Margin" user) + (46 "B.CrtYd" user "B.Courtyard") + (47 "F.CrtYd" user "F.Courtyard") + (48 "B.Fab" user) + (49 "F.Fab" user) + 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