RomeCup-Explorer/boards/panels/explorer-both/.explorer-both.kicad_dru

(version 1)

(rule "Board_0-Minimum Trace Width (outer layer)"
	(constraint track_width (min 5mil))
	(layer outer)
	(condition "A.Type == 'track'"))

(rule "Board_0-Minimum Trace Spacing (outer layer)"
	(constraint clearance (min 5mil))
	(layer outer)
	(condition "A.Type == 'track' && B.Type == A.Type"))

(rule "Board_0-Minimum Trace Width and Spacing (inner layer)"
	(constraint track_width (min 3.5mil))
	(layer inner)
	(condition "A.Type == 'track'"))

(rule "Board_0-Minimum Trace Spacing (inner layer)"
	(constraint clearance (min 3.5mil))
	(layer inner)
	(condition "A.Type == 'track' && B.Type == A.Type"))

(rule "Board_0-Minimum Text"
	(constraint text_thickness (min 0.15mm))
	(constraint text_height (min 1mm))
	(layer "?.Silkscreen"))

(rule "Board_0-Pad to Silkscreen"
	(constraint silk_clearance (min 0.15mm))
	(layer outer)
	(condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')"))

(rule "Board_0-Trace to Outline"
	(constraint edge_clearance (min 0.3mm))
	(condition "A.Type == 'track'"))

(rule "Board_0-drill hole size (mechanical)"
	(constraint hole_size (min 0.2mm) (max 6.3mm)))

(rule "Board_0-Minimum Via Hole Size"
	(constraint hole_size (min 0.2mm))
	(condition "A.Type == 'via'"))

(rule "Board_0-Minimum Via Diameter"
	(constraint via_diameter (min 0.45mm))
	(condition "A.Type == 'via'"))

(rule "Board_0-PTH Hole Size"
	(constraint hole_size (min 0.2mm) (max 6.35mm))
	(condition "A.isPlated()"))

(rule "Board_0-Minimum Non-plated Hole Size"
	(constraint hole_size (min 0.5mm))
	(condition "A.Type == 'pad' && !A.isPlated()"))
	
(rule "Board_0-Minimum Castellated Hole Size"
	(constraint hole_size (min 0.6mm))
	(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'"))

(rule "Board_0-hole to hole clearance (different nets)"
	(constraint hole_to_hole (min 0.5mm))
	(condition "A.Net != B.Net"))

(rule "Board_0-via to track clearance"
	(constraint hole_clearance (min 0.254mm))
	(condition "A.Type == 'via' && B.Type == 'track'"))

(rule "Board_0-via to via clearance (same nets)"
	(constraint hole_to_hole (min 0.254mm))
	(condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net"))

(rule "Board_0-pad to pad clearance (with hole, different nets)"
	(constraint hole_to_hole (min 0.5mm))
	(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))

(rule "Board_0-pad to pad clearance (without hole, different nets)"
	(constraint clearance (min 0.127mm))
	(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))

(rule "Board_0-NPTH to Track clearance)"
	(constraint hole_clearance (min 0.254mm))
	(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'"))

(rule "Board_0-PTH to Track clearance)"
	(constraint hole_clearance (min 0.33mm))
	(condition "A.isPlated() && B.Type == 'track'"))

(rule "Board_0-Pad to Track clearance)"
	(constraint clearance (min 0.2mm))
	(condition "A.isPlated() && B.Type == 'track'"))
(rule "Board_1-Minimum Trace Width (outer layer)"
	(constraint track_width (min 5mil))
	(layer outer)
	(condition "A.Type == 'track'"))

(rule "Board_1-Minimum Trace Spacing (outer layer)"
	(constraint clearance (min 5mil))
	(layer outer)
	(condition "A.Type == 'track' && B.Type == A.Type"))

(rule "Board_1-Minimum Trace Width and Spacing (inner layer)"
	(constraint track_width (min 3.5mil))
	(layer inner)
	(condition "A.Type == 'track'"))

(rule "Board_1-Minimum Trace Spacing (inner layer)"
	(constraint clearance (min 3.5mil))
	(layer inner)
	(condition "A.Type == 'track' && B.Type == A.Type"))

(rule "Board_1-Minimum Text"
	(constraint text_thickness (min 0.15mm))
	(constraint text_height (min 1mm))
	(layer "?.Silkscreen"))

(rule "Board_1-Pad to Silkscreen"
	(constraint silk_clearance (min 0.15mm))
	(layer outer)
	(condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')"))

(rule "Board_1-Trace to Outline"
	(constraint edge_clearance (min 0.3mm))
	(condition "A.Type == 'track'"))

(rule "Board_1-drill hole size (mechanical)"
	(constraint hole_size (min 0.2mm) (max 6.3mm)))

(rule "Board_1-Minimum Via Hole Size"
	(constraint hole_size (min 0.2mm))
	(condition "A.Type == 'via'"))

(rule "Board_1-Minimum Via Diameter"
	(constraint via_diameter (min 0.45mm))
	(condition "A.Type == 'via'"))

(rule "Board_1-PTH Hole Size"
	(constraint hole_size (min 0.2mm) (max 6.35mm))
	(condition "A.isPlated()"))

(rule "Board_1-Minimum Non-plated Hole Size"
	(constraint hole_size (min 0.5mm))
	(condition "A.Type == 'pad' && !A.isPlated()"))
	
(rule "Board_1-Minimum Castellated Hole Size"
	(constraint hole_size (min 0.6mm))
	(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'"))

(rule "Board_1-hole to hole clearance (different nets)"
	(constraint hole_to_hole (min 0.5mm))
	(condition "A.Net != B.Net"))

(rule "Board_1-via to track clearance"
	(constraint hole_clearance (min 0.254mm))
	(condition "A.Type == 'via' && B.Type == 'track'"))

(rule "Board_1-via to via clearance (same nets)"
	(constraint hole_to_hole (min 0.254mm))
	(condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net"))

(rule "Board_1-pad to pad clearance (with hole, different nets)"
	(constraint hole_to_hole (min 0.5mm))
	(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))

(rule "Board_1-pad to pad clearance (without hole, different nets)"
	(constraint clearance (min 0.127mm))
	(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))

(rule "Board_1-NPTH to Track clearance)"
	(constraint hole_clearance (min 0.254mm))
	(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'"))

(rule "Board_1-PTH to Track clearance)"
	(constraint hole_clearance (min 0.33mm))
	(condition "A.isPlated() && B.Type == 'track'"))

(rule "Board_1-Pad to Track clearance)"
	(constraint clearance (min 0.2mm))
	(condition "A.isPlated() && B.Type == 'track'"))