add projects for panels
parent
47369351ab
commit
625e4d923b
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@ -0,0 +1,178 @@
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(version 1)
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(rule "Board_0-Minimum Trace Width (outer layer)"
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(constraint track_width (min 5mil))
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(layer outer)
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(condition "A.Type == 'track'"))
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(rule "Board_0-Minimum Trace Spacing (outer layer)"
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(constraint clearance (min 5mil))
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(layer outer)
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(condition "A.Type == 'track' && B.Type == A.Type"))
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(rule "Board_0-Minimum Trace Width and Spacing (inner layer)"
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(constraint track_width (min 3.5mil))
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(layer inner)
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(condition "A.Type == 'track'"))
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(rule "Board_0-Minimum Trace Spacing (inner layer)"
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(constraint clearance (min 3.5mil))
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(layer inner)
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(condition "A.Type == 'track' && B.Type == A.Type"))
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(rule "Board_0-Minimum Text"
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(constraint text_thickness (min 0.15mm))
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(constraint text_height (min 1mm))
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(layer "?.Silkscreen"))
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(rule "Board_0-Pad to Silkscreen"
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(constraint silk_clearance (min 0.15mm))
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(layer outer)
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(condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')"))
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(rule "Board_0-Trace to Outline"
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(constraint edge_clearance (min 0.3mm))
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(condition "A.Type == 'track'"))
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(rule "Board_0-drill hole size (mechanical)"
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(constraint hole_size (min 0.2mm) (max 6.3mm)))
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(rule "Board_0-Minimum Via Hole Size"
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(constraint hole_size (min 0.2mm))
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(condition "A.Type == 'via'"))
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(rule "Board_0-Minimum Via Diameter"
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(constraint via_diameter (min 0.45mm))
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(condition "A.Type == 'via'"))
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(rule "Board_0-PTH Hole Size"
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(constraint hole_size (min 0.2mm) (max 6.35mm))
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(condition "A.isPlated()"))
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(rule "Board_0-Minimum Non-plated Hole Size"
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(constraint hole_size (min 0.5mm))
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(condition "A.Type == 'pad' && !A.isPlated()"))
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(rule "Board_0-Minimum Castellated Hole Size"
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(constraint hole_size (min 0.6mm))
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(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'"))
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(rule "Board_0-hole to hole clearance (different nets)"
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(constraint hole_to_hole (min 0.5mm))
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(condition "A.Net != B.Net"))
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(rule "Board_0-via to track clearance"
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(constraint hole_clearance (min 0.254mm))
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(condition "A.Type == 'via' && B.Type == 'track'"))
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(rule "Board_0-via to via clearance (same nets)"
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(constraint hole_to_hole (min 0.254mm))
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(condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net"))
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(rule "Board_0-pad to pad clearance (with hole, different nets)"
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(constraint hole_to_hole (min 0.5mm))
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(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
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(rule "Board_0-pad to pad clearance (without hole, different nets)"
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(constraint clearance (min 0.127mm))
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(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
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(rule "Board_0-NPTH to Track clearance)"
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(constraint hole_clearance (min 0.254mm))
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(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'"))
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(rule "Board_0-PTH to Track clearance)"
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(constraint hole_clearance (min 0.33mm))
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(condition "A.isPlated() && B.Type == 'track'"))
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(rule "Board_0-Pad to Track clearance)"
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(constraint clearance (min 0.2mm))
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(condition "A.isPlated() && B.Type == 'track'"))
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(rule "Board_1-Minimum Trace Width (outer layer)"
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(constraint track_width (min 5mil))
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(layer outer)
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(condition "A.Type == 'track'"))
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(rule "Board_1-Minimum Trace Spacing (outer layer)"
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(constraint clearance (min 5mil))
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(layer outer)
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(condition "A.Type == 'track' && B.Type == A.Type"))
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(rule "Board_1-Minimum Trace Width and Spacing (inner layer)"
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(constraint track_width (min 3.5mil))
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(layer inner)
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(condition "A.Type == 'track'"))
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(rule "Board_1-Minimum Trace Spacing (inner layer)"
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(constraint clearance (min 3.5mil))
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(layer inner)
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(condition "A.Type == 'track' && B.Type == A.Type"))
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(rule "Board_1-Minimum Text"
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(constraint text_thickness (min 0.15mm))
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(constraint text_height (min 1mm))
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(layer "?.Silkscreen"))
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(rule "Board_1-Pad to Silkscreen"
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(constraint silk_clearance (min 0.15mm))
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(layer outer)
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(condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')"))
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(rule "Board_1-Trace to Outline"
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(constraint edge_clearance (min 0.3mm))
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(condition "A.Type == 'track'"))
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(rule "Board_1-drill hole size (mechanical)"
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(constraint hole_size (min 0.2mm) (max 6.3mm)))
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(rule "Board_1-Minimum Via Hole Size"
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(constraint hole_size (min 0.2mm))
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(condition "A.Type == 'via'"))
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(rule "Board_1-Minimum Via Diameter"
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(constraint via_diameter (min 0.45mm))
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(condition "A.Type == 'via'"))
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(rule "Board_1-PTH Hole Size"
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(constraint hole_size (min 0.2mm) (max 6.35mm))
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(condition "A.isPlated()"))
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(rule "Board_1-Minimum Non-plated Hole Size"
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(constraint hole_size (min 0.5mm))
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(condition "A.Type == 'pad' && !A.isPlated()"))
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(rule "Board_1-Minimum Castellated Hole Size"
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(constraint hole_size (min 0.6mm))
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(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'"))
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(rule "Board_1-hole to hole clearance (different nets)"
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(constraint hole_to_hole (min 0.5mm))
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(condition "A.Net != B.Net"))
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(rule "Board_1-via to track clearance"
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(constraint hole_clearance (min 0.254mm))
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(condition "A.Type == 'via' && B.Type == 'track'"))
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(rule "Board_1-via to via clearance (same nets)"
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(constraint hole_to_hole (min 0.254mm))
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(condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net"))
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(rule "Board_1-pad to pad clearance (with hole, different nets)"
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(constraint hole_to_hole (min 0.5mm))
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(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
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(rule "Board_1-pad to pad clearance (without hole, different nets)"
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(constraint clearance (min 0.127mm))
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(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
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(rule "Board_1-NPTH to Track clearance)"
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(constraint hole_clearance (min 0.254mm))
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(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'"))
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(rule "Board_1-PTH to Track clearance)"
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(constraint hole_clearance (min 0.33mm))
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(condition "A.isPlated() && B.Type == 'track'"))
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(rule "Board_1-Pad to Track clearance)"
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(constraint clearance (min 0.2mm))
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(condition "A.isPlated() && B.Type == 'track'"))
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,405 @@
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{
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"board": {
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"3dviewports": [],
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"design_settings": {
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"defaults": {
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"board_outline_line_width": 0.09999999999999999,
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"copper_line_width": 0.19999999999999998,
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"copper_text_italic": false,
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"copper_text_size_h": 1.5,
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"copper_text_size_v": 1.5,
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"copper_text_thickness": 0.3,
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"copper_text_upright": false,
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"courtyard_line_width": 0.049999999999999996,
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"dimension_precision": 4,
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"dimension_units": 3,
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"dimensions": {
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"arrow_length": 1270000,
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"extension_offset": 500000,
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"keep_text_aligned": true,
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"suppress_zeroes": false,
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"text_position": 0,
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"units_format": 1
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},
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"fab_line_width": 0.09999999999999999,
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"fab_text_italic": false,
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"fab_text_size_h": 1.0,
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"fab_text_size_v": 1.0,
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"fab_text_thickness": 0.15,
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"fab_text_upright": false,
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"other_line_width": 0.15,
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"other_text_italic": false,
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"other_text_size_h": 1.0,
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"other_text_size_v": 1.0,
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"other_text_thickness": 0.15,
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"other_text_upright": false,
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"pads": {
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"drill": 0.762,
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"height": 1.524,
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"width": 1.524
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},
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"silk_line_width": 0.15,
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"silk_text_italic": false,
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"silk_text_size_h": 1.0,
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"silk_text_size_v": 1.0,
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"silk_text_thickness": 0.15,
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"silk_text_upright": false,
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"zones": {
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"min_clearance": 0.5
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}
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},
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"diff_pair_dimensions": [
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{
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"gap": 0.0,
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"via_gap": 0.0,
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"width": 0.0
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}
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],
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"drc_exclusions": [],
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"meta": {
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"version": 2
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},
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"rule_severities": {
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"annular_width": "error",
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"clearance": "error",
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"connection_width": "warning",
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"copper_edge_clearance": "error",
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"copper_sliver": "warning",
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"courtyards_overlap": "error",
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"diff_pair_gap_out_of_range": "error",
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"diff_pair_uncoupled_length_too_long": "error",
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"drill_out_of_range": "error",
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"duplicate_footprints": "warning",
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"extra_footprint": "warning",
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"footprint": "error",
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"footprint_type_mismatch": "ignore",
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"hole_clearance": "error",
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"hole_near_hole": "error",
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"invalid_outline": "error",
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"isolated_copper": "warning",
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"item_on_disabled_layer": "error",
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"items_not_allowed": "error",
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"length_out_of_range": "error",
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"lib_footprint_issues": "warning",
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"lib_footprint_mismatch": "warning",
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"malformed_courtyard": "error",
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"microvia_drill_out_of_range": "error",
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"missing_courtyard": "ignore",
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"missing_footprint": "warning",
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"net_conflict": "warning",
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"npth_inside_courtyard": "ignore",
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"padstack": "warning",
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"pth_inside_courtyard": "ignore",
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"shorting_items": "error",
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"silk_edge_clearance": "warning",
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"silk_over_copper": "warning",
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"silk_overlap": "warning",
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"skew_out_of_range": "error",
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"solder_mask_bridge": "error",
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"starved_thermal": "error",
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"text_height": "warning",
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"text_thickness": "warning",
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"through_hole_pad_without_hole": "error",
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"too_many_vias": "error",
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"track_dangling": "warning",
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"track_width": "error",
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"tracks_crossing": "error",
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"unconnected_items": "error",
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"unresolved_variable": "error",
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"via_dangling": "warning",
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"zones_intersect": "error"
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},
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"rules": {
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"max_error": 0.005,
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"min_clearance": 0.0,
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"min_connection": 0.0,
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"min_copper_edge_clearance": 0.0,
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"min_hole_clearance": 0.25,
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"min_hole_to_hole": 0.25,
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"min_microvia_diameter": 0.19999999999999998,
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"min_microvia_drill": 0.09999999999999999,
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"min_resolved_spokes": 2,
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"min_silk_clearance": 0.0,
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"min_text_height": 0.7999999999999999,
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"min_text_thickness": 0.08,
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"min_through_hole_diameter": 0.3,
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"min_track_width": 0.0,
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"min_via_annular_width": 0.09999999999999999,
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"min_via_diameter": 0.5,
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"solder_mask_clearance": 0.0,
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"solder_mask_min_width": 0.0,
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"solder_mask_to_copper_clearance": 0.0,
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"use_height_for_length_calcs": true
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},
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"teardrop_options": [
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{
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"td_allow_use_two_tracks": false,
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"td_curve_segcount": 5,
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"td_on_pad_in_zone": false,
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"td_onpadsmd": false,
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"td_onroundshapesonly": false,
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"td_ontrackend": true,
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"td_onviapad": false
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}
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],
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"teardrop_parameters": [
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{
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"td_curve_segcount": 5,
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"td_height_ratio": 1.0,
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"td_length_ratio": 0.5,
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"td_maxheight": 2.0,
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"td_maxlen": 1.0,
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"td_target_name": "td_round_shape",
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"td_width_to_size_filter_ratio": 0.9
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},
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{
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"td_curve_segcount": 5,
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"td_height_ratio": 1.0,
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"td_length_ratio": 0.5,
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"td_maxheight": 2.0,
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"td_maxlen": 1.0,
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"td_target_name": "td_rect_shape",
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"td_width_to_size_filter_ratio": 0.9
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},
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{
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"td_curve_segcount": 5,
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"td_height_ratio": 1.0,
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"td_length_ratio": 0.5,
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"td_maxheight": 3.0,
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"td_maxlen": 1.0,
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"td_target_name": "td_track_end",
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"td_width_to_size_filter_ratio": 0.9
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}
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],
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"track_widths": [
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0.0,
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0.2,
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0.3,
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0.4,
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0.8
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],
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"via_dimensions": [
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{
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"diameter": 0.0,
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"drill": 0.0
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}
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],
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"zones_allow_external_fillets": false
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},
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"layer_presets": [],
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"viewports": []
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},
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"boards": [],
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"cvpcb": {
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"equivalence_files": []
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},
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"libraries": {
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"pinned_footprint_libs": [],
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"pinned_symbol_libs": []
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},
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"meta": {
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"filename": ".explorer-both.kicad_pro",
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"version": 1
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},
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"net_settings": {
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"classes": [
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{
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"bus_width": 12,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "Default",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.35,
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"via_diameter": 0.8,
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"via_drill": 0.4,
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"wire_width": 6
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},
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{
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"bus_width": 12,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "power",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 1.0,
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"via_diameter": 0.8,
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"via_drill": 0.4,
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"wire_width": 6
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},
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{
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"bus_width": 12,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
|
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "Board_0-Default",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.35,
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"via_diameter": 0.8,
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"via_drill": 0.4,
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"wire_width": 6
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},
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{
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"bus_width": 12,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Board_0-power",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 1.0,
|
||||
"via_diameter": 0.8,
|
||||
"via_drill": 0.4,
|
||||
"wire_width": 6
|
||||
},
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Board_1-Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 1.0,
|
||||
"via_diameter": 0.8,
|
||||
"via_drill": 0.4,
|
||||
"wire_width": 6
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 3
|
||||
},
|
||||
"net_colors": null,
|
||||
"netclass_assignments": null,
|
||||
"netclass_patterns": [
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-/DAC_OUT"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-Net-(IC2-+INPUT)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-unconnected-(IC1-PA3{slash}EXTCLK-Pad7)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-Net-(IC2-GAIN_2)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-Net-(C10-Pad1)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-unconnected-(IC1-PA2-Pad5)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-/FILTER_OUT"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-Net-(IC2-GAIN_1)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-unconnected-(IC2-BYPASS-Pad7)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-Net-(JPROG1-Pin_3)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-Net-(C5-Pad2)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-unconnected-(IC1-PA1-Pad4)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-unconnected-(IC1-PA7-Pad3)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-/PROG"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-Net-(C1-Pad1)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-power",
|
||||
"pattern": "Board_0-VCC"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-power",
|
||||
"pattern": "Board_0-GND"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-power",
|
||||
"pattern": "Board_0-/PWR"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-power",
|
||||
"pattern": "Board_0-/AUDIO_OUT*"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_1-Default",
|
||||
"pattern": "Board_1-Net-(D1-K)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_1-Default",
|
||||
"pattern": "Board_1-VCC"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_1-Default",
|
||||
"pattern": "Board_1-GND"
|
||||
}
|
||||
]
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": []
|
||||
},
|
||||
"sheets": [],
|
||||
"text_variables": {}
|
||||
}
|
|
@ -0,0 +1,178 @@
|
|||
(version 1)
|
||||
|
||||
(rule "Board_0-Minimum Trace Width (outer layer)"
|
||||
(constraint track_width (min 5mil))
|
||||
(layer outer)
|
||||
(condition "A.Type == 'track'"))
|
||||
|
||||
(rule "Board_0-Minimum Trace Spacing (outer layer)"
|
||||
(constraint clearance (min 5mil))
|
||||
(layer outer)
|
||||
(condition "A.Type == 'track' && B.Type == A.Type"))
|
||||
|
||||
(rule "Board_0-Minimum Trace Width and Spacing (inner layer)"
|
||||
(constraint track_width (min 3.5mil))
|
||||
(layer inner)
|
||||
(condition "A.Type == 'track'"))
|
||||
|
||||
(rule "Board_0-Minimum Trace Spacing (inner layer)"
|
||||
(constraint clearance (min 3.5mil))
|
||||
(layer inner)
|
||||
(condition "A.Type == 'track' && B.Type == A.Type"))
|
||||
|
||||
(rule "Board_0-Minimum Text"
|
||||
(constraint text_thickness (min 0.15mm))
|
||||
(constraint text_height (min 1mm))
|
||||
(layer "?.Silkscreen"))
|
||||
|
||||
(rule "Board_0-Pad to Silkscreen"
|
||||
(constraint silk_clearance (min 0.15mm))
|
||||
(layer outer)
|
||||
(condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')"))
|
||||
|
||||
(rule "Board_0-Trace to Outline"
|
||||
(constraint edge_clearance (min 0.3mm))
|
||||
(condition "A.Type == 'track'"))
|
||||
|
||||
(rule "Board_0-drill hole size (mechanical)"
|
||||
(constraint hole_size (min 0.2mm) (max 6.3mm)))
|
||||
|
||||
(rule "Board_0-Minimum Via Hole Size"
|
||||
(constraint hole_size (min 0.2mm))
|
||||
(condition "A.Type == 'via'"))
|
||||
|
||||
(rule "Board_0-Minimum Via Diameter"
|
||||
(constraint via_diameter (min 0.45mm))
|
||||
(condition "A.Type == 'via'"))
|
||||
|
||||
(rule "Board_0-PTH Hole Size"
|
||||
(constraint hole_size (min 0.2mm) (max 6.35mm))
|
||||
(condition "A.isPlated()"))
|
||||
|
||||
(rule "Board_0-Minimum Non-plated Hole Size"
|
||||
(constraint hole_size (min 0.5mm))
|
||||
(condition "A.Type == 'pad' && !A.isPlated()"))
|
||||
|
||||
(rule "Board_0-Minimum Castellated Hole Size"
|
||||
(constraint hole_size (min 0.6mm))
|
||||
(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'"))
|
||||
|
||||
(rule "Board_0-hole to hole clearance (different nets)"
|
||||
(constraint hole_to_hole (min 0.5mm))
|
||||
(condition "A.Net != B.Net"))
|
||||
|
||||
(rule "Board_0-via to track clearance"
|
||||
(constraint hole_clearance (min 0.254mm))
|
||||
(condition "A.Type == 'via' && B.Type == 'track'"))
|
||||
|
||||
(rule "Board_0-via to via clearance (same nets)"
|
||||
(constraint hole_to_hole (min 0.254mm))
|
||||
(condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net"))
|
||||
|
||||
(rule "Board_0-pad to pad clearance (with hole, different nets)"
|
||||
(constraint hole_to_hole (min 0.5mm))
|
||||
(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
|
||||
|
||||
(rule "Board_0-pad to pad clearance (without hole, different nets)"
|
||||
(constraint clearance (min 0.127mm))
|
||||
(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
|
||||
|
||||
(rule "Board_0-NPTH to Track clearance)"
|
||||
(constraint hole_clearance (min 0.254mm))
|
||||
(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'"))
|
||||
|
||||
(rule "Board_0-PTH to Track clearance)"
|
||||
(constraint hole_clearance (min 0.33mm))
|
||||
(condition "A.isPlated() && B.Type == 'track'"))
|
||||
|
||||
(rule "Board_0-Pad to Track clearance)"
|
||||
(constraint clearance (min 0.2mm))
|
||||
(condition "A.isPlated() && B.Type == 'track'"))
|
||||
(rule "Board_1-Minimum Trace Width (outer layer)"
|
||||
(constraint track_width (min 5mil))
|
||||
(layer outer)
|
||||
(condition "A.Type == 'track'"))
|
||||
|
||||
(rule "Board_1-Minimum Trace Spacing (outer layer)"
|
||||
(constraint clearance (min 5mil))
|
||||
(layer outer)
|
||||
(condition "A.Type == 'track' && B.Type == A.Type"))
|
||||
|
||||
(rule "Board_1-Minimum Trace Width and Spacing (inner layer)"
|
||||
(constraint track_width (min 3.5mil))
|
||||
(layer inner)
|
||||
(condition "A.Type == 'track'"))
|
||||
|
||||
(rule "Board_1-Minimum Trace Spacing (inner layer)"
|
||||
(constraint clearance (min 3.5mil))
|
||||
(layer inner)
|
||||
(condition "A.Type == 'track' && B.Type == A.Type"))
|
||||
|
||||
(rule "Board_1-Minimum Text"
|
||||
(constraint text_thickness (min 0.15mm))
|
||||
(constraint text_height (min 1mm))
|
||||
(layer "?.Silkscreen"))
|
||||
|
||||
(rule "Board_1-Pad to Silkscreen"
|
||||
(constraint silk_clearance (min 0.15mm))
|
||||
(layer outer)
|
||||
(condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'graphic')"))
|
||||
|
||||
(rule "Board_1-Trace to Outline"
|
||||
(constraint edge_clearance (min 0.3mm))
|
||||
(condition "A.Type == 'track'"))
|
||||
|
||||
(rule "Board_1-drill hole size (mechanical)"
|
||||
(constraint hole_size (min 0.2mm) (max 6.3mm)))
|
||||
|
||||
(rule "Board_1-Minimum Via Hole Size"
|
||||
(constraint hole_size (min 0.2mm))
|
||||
(condition "A.Type == 'via'"))
|
||||
|
||||
(rule "Board_1-Minimum Via Diameter"
|
||||
(constraint via_diameter (min 0.45mm))
|
||||
(condition "A.Type == 'via'"))
|
||||
|
||||
(rule "Board_1-PTH Hole Size"
|
||||
(constraint hole_size (min 0.2mm) (max 6.35mm))
|
||||
(condition "A.isPlated()"))
|
||||
|
||||
(rule "Board_1-Minimum Non-plated Hole Size"
|
||||
(constraint hole_size (min 0.5mm))
|
||||
(condition "A.Type == 'pad' && !A.isPlated()"))
|
||||
|
||||
(rule "Board_1-Minimum Castellated Hole Size"
|
||||
(constraint hole_size (min 0.6mm))
|
||||
(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'"))
|
||||
|
||||
(rule "Board_1-hole to hole clearance (different nets)"
|
||||
(constraint hole_to_hole (min 0.5mm))
|
||||
(condition "A.Net != B.Net"))
|
||||
|
||||
(rule "Board_1-via to track clearance"
|
||||
(constraint hole_clearance (min 0.254mm))
|
||||
(condition "A.Type == 'via' && B.Type == 'track'"))
|
||||
|
||||
(rule "Board_1-via to via clearance (same nets)"
|
||||
(constraint hole_to_hole (min 0.254mm))
|
||||
(condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net"))
|
||||
|
||||
(rule "Board_1-pad to pad clearance (with hole, different nets)"
|
||||
(constraint hole_to_hole (min 0.5mm))
|
||||
(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
|
||||
|
||||
(rule "Board_1-pad to pad clearance (without hole, different nets)"
|
||||
(constraint clearance (min 0.127mm))
|
||||
(condition "A.Type == 'pad' && B.Type == A.Type && A.Net != B.Net"))
|
||||
|
||||
(rule "Board_1-NPTH to Track clearance)"
|
||||
(constraint hole_clearance (min 0.254mm))
|
||||
(condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'"))
|
||||
|
||||
(rule "Board_1-PTH to Track clearance)"
|
||||
(constraint hole_clearance (min 0.33mm))
|
||||
(condition "A.isPlated() && B.Type == 'track'"))
|
||||
|
||||
(rule "Board_1-Pad to Track clearance)"
|
||||
(constraint clearance (min 0.2mm))
|
||||
(condition "A.isPlated() && B.Type == 'track'"))
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,405 @@
|
|||
{
|
||||
"board": {
|
||||
"3dviewports": [],
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"board_outline_line_width": 0.09999999999999999,
|
||||
"copper_line_width": 0.19999999999999998,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.5,
|
||||
"copper_text_size_v": 1.5,
|
||||
"copper_text_thickness": 0.3,
|
||||
"copper_text_upright": false,
|
||||
"courtyard_line_width": 0.049999999999999996,
|
||||
"dimension_precision": 4,
|
||||
"dimension_units": 3,
|
||||
"dimensions": {
|
||||
"arrow_length": 1270000,
|
||||
"extension_offset": 500000,
|
||||
"keep_text_aligned": true,
|
||||
"suppress_zeroes": false,
|
||||
"text_position": 0,
|
||||
"units_format": 1
|
||||
},
|
||||
"fab_line_width": 0.09999999999999999,
|
||||
"fab_text_italic": false,
|
||||
"fab_text_size_h": 1.0,
|
||||
"fab_text_size_v": 1.0,
|
||||
"fab_text_thickness": 0.15,
|
||||
"fab_text_upright": false,
|
||||
"other_line_width": 0.15,
|
||||
"other_text_italic": false,
|
||||
"other_text_size_h": 1.0,
|
||||
"other_text_size_v": 1.0,
|
||||
"other_text_thickness": 0.15,
|
||||
"other_text_upright": false,
|
||||
"pads": {
|
||||
"drill": 0.762,
|
||||
"height": 1.524,
|
||||
"width": 1.524
|
||||
},
|
||||
"silk_line_width": 0.15,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
"silk_text_thickness": 0.15,
|
||||
"silk_text_upright": false,
|
||||
"zones": {
|
||||
"min_clearance": 0.5
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [
|
||||
{
|
||||
"gap": 0.0,
|
||||
"via_gap": 0.0,
|
||||
"width": 0.0
|
||||
}
|
||||
],
|
||||
"drc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"rule_severities": {
|
||||
"annular_width": "error",
|
||||
"clearance": "error",
|
||||
"connection_width": "warning",
|
||||
"copper_edge_clearance": "error",
|
||||
"copper_sliver": "warning",
|
||||
"courtyards_overlap": "error",
|
||||
"diff_pair_gap_out_of_range": "error",
|
||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
|
||||
"duplicate_footprints": "warning",
|
||||
"extra_footprint": "warning",
|
||||
"footprint": "error",
|
||||
"footprint_type_mismatch": "ignore",
|
||||
"hole_clearance": "error",
|
||||
"hole_near_hole": "error",
|
||||
"invalid_outline": "error",
|
||||
"isolated_copper": "warning",
|
||||
"item_on_disabled_layer": "error",
|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
"lib_footprint_issues": "warning",
|
||||
"lib_footprint_mismatch": "warning",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"missing_courtyard": "ignore",
|
||||
"missing_footprint": "warning",
|
||||
"net_conflict": "warning",
|
||||
"npth_inside_courtyard": "ignore",
|
||||
"padstack": "warning",
|
||||
"pth_inside_courtyard": "ignore",
|
||||
"shorting_items": "error",
|
||||
"silk_edge_clearance": "warning",
|
||||
"silk_over_copper": "warning",
|
||||
"silk_overlap": "warning",
|
||||
"skew_out_of_range": "error",
|
||||
"solder_mask_bridge": "error",
|
||||
"starved_thermal": "error",
|
||||
"text_height": "warning",
|
||||
"text_thickness": "warning",
|
||||
"through_hole_pad_without_hole": "error",
|
||||
"too_many_vias": "error",
|
||||
"track_dangling": "warning",
|
||||
"track_width": "error",
|
||||
"tracks_crossing": "error",
|
||||
"unconnected_items": "error",
|
||||
"unresolved_variable": "error",
|
||||
"via_dangling": "warning",
|
||||
"zones_intersect": "error"
|
||||
},
|
||||
"rules": {
|
||||
"max_error": 0.005,
|
||||
"min_clearance": 0.0,
|
||||
"min_connection": 0.0,
|
||||
"min_copper_edge_clearance": 0.0,
|
||||
"min_hole_clearance": 0.25,
|
||||
"min_hole_to_hole": 0.25,
|
||||
"min_microvia_diameter": 0.19999999999999998,
|
||||
"min_microvia_drill": 0.09999999999999999,
|
||||
"min_resolved_spokes": 2,
|
||||
"min_silk_clearance": 0.0,
|
||||
"min_text_height": 0.7999999999999999,
|
||||
"min_text_thickness": 0.08,
|
||||
"min_through_hole_diameter": 0.3,
|
||||
"min_track_width": 0.0,
|
||||
"min_via_annular_width": 0.09999999999999999,
|
||||
"min_via_diameter": 0.5,
|
||||
"solder_mask_clearance": 0.0,
|
||||
"solder_mask_min_width": 0.0,
|
||||
"solder_mask_to_copper_clearance": 0.0,
|
||||
"use_height_for_length_calcs": true
|
||||
},
|
||||
"teardrop_options": [
|
||||
{
|
||||
"td_allow_use_two_tracks": false,
|
||||
"td_curve_segcount": 5,
|
||||
"td_on_pad_in_zone": false,
|
||||
"td_onpadsmd": false,
|
||||
"td_onroundshapesonly": false,
|
||||
"td_ontrackend": true,
|
||||
"td_onviapad": false
|
||||
}
|
||||
],
|
||||
"teardrop_parameters": [
|
||||
{
|
||||
"td_curve_segcount": 5,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 2.0,
|
||||
"td_maxlen": 1.0,
|
||||
"td_target_name": "td_round_shape",
|
||||
"td_width_to_size_filter_ratio": 0.9
|
||||
},
|
||||
{
|
||||
"td_curve_segcount": 5,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 2.0,
|
||||
"td_maxlen": 1.0,
|
||||
"td_target_name": "td_rect_shape",
|
||||
"td_width_to_size_filter_ratio": 0.9
|
||||
},
|
||||
{
|
||||
"td_curve_segcount": 5,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 3.0,
|
||||
"td_maxlen": 1.0,
|
||||
"td_target_name": "td_track_end",
|
||||
"td_width_to_size_filter_ratio": 0.9
|
||||
}
|
||||
],
|
||||
"track_widths": [
|
||||
0.0,
|
||||
0.2,
|
||||
0.3,
|
||||
0.4,
|
||||
0.8
|
||||
],
|
||||
"via_dimensions": [
|
||||
{
|
||||
"diameter": 0.0,
|
||||
"drill": 0.0
|
||||
}
|
||||
],
|
||||
"zones_allow_external_fillets": false
|
||||
},
|
||||
"layer_presets": [],
|
||||
"viewports": []
|
||||
},
|
||||
"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "explorer-both.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.35,
|
||||
"via_diameter": 0.8,
|
||||
"via_drill": 0.4,
|
||||
"wire_width": 6
|
||||
},
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Board_0-Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.35,
|
||||
"via_diameter": 0.8,
|
||||
"via_drill": 0.4,
|
||||
"wire_width": 6
|
||||
},
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Board_0-power",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 1.0,
|
||||
"via_diameter": 0.8,
|
||||
"via_drill": 0.4,
|
||||
"wire_width": 6
|
||||
},
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Board_1-Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 1.0,
|
||||
"via_diameter": 0.8,
|
||||
"via_drill": 0.4,
|
||||
"wire_width": 6
|
||||
},
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "power",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 1.0,
|
||||
"via_diameter": 0.8,
|
||||
"via_drill": 0.4,
|
||||
"wire_width": 6
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 3
|
||||
},
|
||||
"net_colors": null,
|
||||
"netclass_assignments": null,
|
||||
"netclass_patterns": [
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-unconnected-(IC1-PA1-Pad4)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-Net-(IC2-+INPUT)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-/PROG"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-unconnected-(IC1-PA3{slash}EXTCLK-Pad7)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-unconnected-(IC1-PA2-Pad5)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-unconnected-(IC2-BYPASS-Pad7)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-unconnected-(IC1-PA7-Pad3)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-/DAC_OUT"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-Net-(C1-Pad1)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-Net-(C5-Pad2)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-Net-(IC2-GAIN_1)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-Net-(IC2-GAIN_2)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-Net-(JPROG1-Pin_3)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-/FILTER_OUT"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-Default",
|
||||
"pattern": "Board_0-Net-(C10-Pad1)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-power",
|
||||
"pattern": "Board_0-VCC"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-power",
|
||||
"pattern": "Board_0-GND"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-power",
|
||||
"pattern": "Board_0-/PWR"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_0-power",
|
||||
"pattern": "Board_0-/AUDIO_OUT*"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_1-Default",
|
||||
"pattern": "Board_1-Net-(D1-K)"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_1-Default",
|
||||
"pattern": "Board_1-GND"
|
||||
},
|
||||
{
|
||||
"netclass": "Board_1-Default",
|
||||
"pattern": "Board_1-VCC"
|
||||
}
|
||||
]
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": []
|
||||
},
|
||||
"sheets": [],
|
||||
"text_variables": {}
|
||||
}
|
Binary file not shown.
|
@ -0,0 +1,114 @@
|
|||
from kikit import panelize_ui_impl as ki
|
||||
from kikit.units import mm, deg
|
||||
from kikit.panelize import Panel, BasicGridPosition, Origin
|
||||
from pcbnewTransition.pcbnew import LoadBoard, VECTOR2I
|
||||
from pcbnewTransition import pcbnew
|
||||
from itertools import chain
|
||||
|
||||
|
||||
|
||||
############### Custom config
|
||||
board1_path = "../explorer/explorer.kicad_pcb"
|
||||
board2_path = "../explorer-light/explorer-light.kicad_pcb"
|
||||
output_path = "./explorer-both.kicad_pcb"
|
||||
|
||||
board_spacing = 3*mm
|
||||
|
||||
################ KiKit Panel Config (Only deviations from default)
|
||||
|
||||
framing={
|
||||
"type": "none" #only rail on top and bottom
|
||||
}
|
||||
|
||||
cuts = {
|
||||
"type": "mousebites"
|
||||
}
|
||||
tabs = { #Add tabs between board and board as well as board and rail
|
||||
"type":"spacing", #Place them with constant width and spacing
|
||||
"vwidth": "5mm",
|
||||
"spacing" : "5mm"
|
||||
}
|
||||
tooling = {
|
||||
"type": "none"
|
||||
}
|
||||
|
||||
# Obtain full config by combining above with default
|
||||
preset = ki.obtainPreset([], tabs=tabs, cuts=cuts, framing=framing, tooling=tooling)
|
||||
|
||||
|
||||
|
||||
################ Adjusted `panelize_ui#doPanelization`
|
||||
|
||||
# Prepare
|
||||
board1 = LoadBoard(board1_path)
|
||||
board2 = LoadBoard(board2_path)
|
||||
panel = Panel(output_path)
|
||||
|
||||
|
||||
panel.inheritDesignSettings(board1)
|
||||
panel.inheritProperties(board1)
|
||||
panel.inheritTitleBlock(board1)
|
||||
|
||||
|
||||
|
||||
|
||||
###### Manually build layout. Inspired by `panelize_ui_impl#buildLayout`
|
||||
sourceArea1 = ki.readSourceArea(preset["source"], board1)
|
||||
sourceArea2 = ki.readSourceArea(preset["source"], board2)
|
||||
|
||||
substrateCount = len(panel.substrates) # Store number of previous boards (probably 0)
|
||||
# Prepare renaming nets and references
|
||||
netRenamer = lambda x, y: "Board_{n}-{orig}".format(n=x, orig=y)
|
||||
#refRenamer = lambda x, y: "Board_{n}-{orig}".format(n=x, orig=y)
|
||||
refRenamer = lambda x, y: x*"_" + "{orig}".format(n=x, orig=y)
|
||||
# I want to mantain the silkscreen as in original. I will prepend n zero-width joiner
|
||||
# characters to mantain the appearances but give them different names
|
||||
#netRenamer = lambda x, y: x*b"".decode("utf-8") + "{orig}".format(n=x, orig=y)
|
||||
#refRenamer = lambda x, y: x*b"".decode("utf-8") + "{orig}".format(n=x, orig=y)
|
||||
|
||||
# Actually place the individual boards
|
||||
# Use existing grid positioner
|
||||
# Place two boards above each other
|
||||
panelOrigin = VECTOR2I(0,0)
|
||||
placer = BasicGridPosition(board_spacing, board_spacing) #HorSpace, VerSpace
|
||||
area1 = panel.appendBoard(board1_path, panelOrigin + placer.position(0,0, None) , origin=Origin.Center, sourceArea=sourceArea1, netRenamer=netRenamer, refRenamer=refRenamer)
|
||||
area2 = panel.appendBoard(board2_path, panelOrigin + placer.position(1,0, area1), origin=Origin.Center, sourceArea=sourceArea2, netRenamer=netRenamer, refRenamer=refRenamer, inheritDrc=False)
|
||||
|
||||
|
||||
substrates = panel.substrates[substrateCount:] # Collect set of newly added boards
|
||||
|
||||
# Prepare frame and partition
|
||||
framingSubstrates = ki.dummyFramingSubstrate(substrates, preset)
|
||||
panel.buildPartitionLineFromBB(framingSubstrates)
|
||||
backboneCuts = ki.buildBackBone(preset["layout"], panel, substrates, preset)
|
||||
|
||||
|
||||
######## --------------------- Continue doPanelization
|
||||
|
||||
tabCuts = ki.buildTabs(preset, panel, substrates, framingSubstrates)
|
||||
|
||||
frameCuts = ki.buildFraming(preset, panel)
|
||||
|
||||
|
||||
ki.buildTooling(preset, panel)
|
||||
ki.buildFiducials(preset, panel)
|
||||
for textSection in ["text", "text2", "text3", "text4"]:
|
||||
ki.buildText(preset[textSection], panel)
|
||||
ki.buildPostprocessing(preset["post"], panel)
|
||||
|
||||
ki.makeTabCuts(preset, panel, tabCuts)
|
||||
ki.makeOtherCuts(preset, panel, chain(backboneCuts, frameCuts))
|
||||
|
||||
|
||||
ki.buildCopperfill(preset["copperfill"], panel)
|
||||
|
||||
ki.setStackup(preset["source"], panel)
|
||||
ki.setPageSize(preset["page"], panel, board1)
|
||||
ki.positionPanel(preset["page"], panel)
|
||||
|
||||
ki.runUserScript(preset["post"], panel)
|
||||
|
||||
ki.buildDebugAnnotation(preset["debug"], panel)
|
||||
|
||||
panel.save(reconstructArcs=preset["post"]["reconstructarcs"],
|
||||
refillAllZones=preset["post"]["refillzones"])
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,472 @@
|
|||
{
|
||||
"board": {
|
||||
"3dviewports": [],
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"board_outline_line_width": 0.049999999999999996,
|
||||
"copper_line_width": 0.19999999999999998,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.5,
|
||||
"copper_text_size_v": 1.5,
|
||||
"copper_text_thickness": 0.3,
|
||||
"copper_text_upright": false,
|
||||
"courtyard_line_width": 0.049999999999999996,
|
||||
"dimension_precision": 4,
|
||||
"dimension_units": 3,
|
||||
"dimensions": {
|
||||
"arrow_length": 1270000,
|
||||
"extension_offset": 500000,
|
||||
"keep_text_aligned": true,
|
||||
"suppress_zeroes": false,
|
||||
"text_position": 0,
|
||||
"units_format": 1
|
||||
},
|
||||
"fab_line_width": 0.09999999999999999,
|
||||
"fab_text_italic": false,
|
||||
"fab_text_size_h": 1.0,
|
||||
"fab_text_size_v": 1.0,
|
||||
"fab_text_thickness": 0.15,
|
||||
"fab_text_upright": false,
|
||||
"other_line_width": 0.09999999999999999,
|
||||
"other_text_italic": false,
|
||||
"other_text_size_h": 1.0,
|
||||
"other_text_size_v": 1.0,
|
||||
"other_text_thickness": 0.15,
|
||||
"other_text_upright": false,
|
||||
"pads": {
|
||||
"drill": 0.762,
|
||||
"height": 1.524,
|
||||
"width": 1.524
|
||||
},
|
||||
"silk_line_width": 0.09999999999999999,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
"silk_text_thickness": 0.09999999999999999,
|
||||
"silk_text_upright": false,
|
||||
"zones": {
|
||||
"min_clearance": 0.5
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [],
|
||||
"drc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"rule_severities": {
|
||||
"annular_width": "error",
|
||||
"clearance": "error",
|
||||
"connection_width": "warning",
|
||||
"copper_edge_clearance": "error",
|
||||
"copper_sliver": "warning",
|
||||
"courtyards_overlap": "error",
|
||||
"diff_pair_gap_out_of_range": "error",
|
||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
|
||||
"duplicate_footprints": "warning",
|
||||
"extra_footprint": "warning",
|
||||
"footprint": "error",
|
||||
"footprint_type_mismatch": "ignore",
|
||||
"hole_clearance": "error",
|
||||
"hole_near_hole": "error",
|
||||
"invalid_outline": "error",
|
||||
"isolated_copper": "warning",
|
||||
"item_on_disabled_layer": "error",
|
||||
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Binary file not shown.
Binary file not shown.
|
@ -0,0 +1,9 @@
|
|||
Ordering Instructions:
|
||||
Panel dimensions: 98.26 x 136.63 mm.
|
||||
Solder Mask: Red (Default)
|
||||
Silkscreen: White (Default)
|
||||
Layers: 2
|
||||
Finish: HASL Lead-free (Default)
|
||||
Thickness: 1.6mm (Default)
|
||||
Copper weight: 1oz (Default)
|
||||
Minimum track width: 0.30mm (11.81mil)
|
|
@ -0,0 +1,15 @@
|
|||
{
|
||||
"dimensionsInchesBtn": true,
|
||||
"dimensionsMmBtn": false,
|
||||
"panelSizeSmallerBtn": true,
|
||||
"panelSizeLargerBtn": false,
|
||||
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|
||||
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|
||||
"gapsVerticalCtrl": "0.0",
|
||||
"gapsHorizontalCtrl": "0.0",
|
||||
"removeRightVerticalCheck": false,
|
||||
"productionBordersCheck": false,
|
||||
"productionFiducialsCheck": false,
|
||||
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|
||||
"vScoreLayer": "User.Comments"
|
||||
}
|
|
@ -0,0 +1,8 @@
|
|||
2024-03-02 21:58:01,642 - panelizer_logger - WARNING -
|
||||
START: 2024-03-02T21:57:57.962560
|
||||
|
||||
Board: /home/emamaker/work/fmd/romecup2024/explorer-panel/Production/explorer-panel_panelized.kicad_pcb
|
||||
Board dimensions: 98.26 x 68.06 mm.
|
||||
You can fit 1 x 2 boards on the panel.
|
||||
Ordering Instructions not found! No futher ordering warnings will be given.
|
||||
|
File diff suppressed because it is too large
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|
@ -0,0 +1,472 @@
|
|||
{
|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"global_label_dangling": "warning",
|
||||
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|
||||
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|
||||
"lib_symbol_issues": "warning",
|
||||
"missing_bidi_pin": "warning",
|
||||
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|
||||
"missing_power_pin": "error",
|
||||
"missing_unit": "warning",
|
||||
"multiple_net_names": "warning",
|
||||
"net_not_bus_member": "warning",
|
||||
"no_connect_connected": "warning",
|
||||
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|
||||
"pin_not_connected": "error",
|
||||
"pin_not_driven": "error",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"wire_dangling": "error"
|
||||
}
|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
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|
||||
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|
||||
{
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"name": "Default",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 3
|
||||
},
|
||||
"net_colors": null,
|
||||
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|
||||
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|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"annotate_start_num": 0,
|
||||
"drawing": {
|
||||
"dashed_lines_dash_length_ratio": 12.0,
|
||||
"dashed_lines_gap_length_ratio": 3.0,
|
||||
"default_line_thickness": 6.0,
|
||||
"default_text_size": 50.0,
|
||||
"field_names": [],
|
||||
"intersheets_ref_own_page": false,
|
||||
"intersheets_ref_prefix": "",
|
||||
"intersheets_ref_short": false,
|
||||
"intersheets_ref_show": false,
|
||||
"intersheets_ref_suffix": "",
|
||||
"junction_size_choice": 3,
|
||||
"label_size_ratio": 0.375,
|
||||
"pin_symbol_size": 25.0,
|
||||
"text_offset_ratio": 0.15
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_format_name": "",
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"spice_current_sheet_as_root": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"spice_model_current_sheet_as_root": true,
|
||||
"spice_save_all_currents": false,
|
||||
"spice_save_all_voltages": false,
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
"sheets": [],
|
||||
"text_variables": {}
|
||||
}
|
|
@ -0,0 +1,5 @@
|
|||
(kicad_sch (version 20230121) (generator eeschema)
|
||||
(paper "A4")
|
||||
(lib_symbols)
|
||||
(symbol_instances)
|
||||
)
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,803 @@
|
|||
%TF.GenerationSoftware,KiCad,Pcbnew,7.0.10*%
|
||||
%TF.CreationDate,2024-03-03T12:06:43+01:00*%
|
||||
%TF.ProjectId,explorer-panel,6578706c-6f72-4657-922d-70616e656c2e,rev?*%
|
||||
%TF.SameCoordinates,Original*%
|
||||
%TF.FileFunction,Soldermask,Bot*%
|
||||
%TF.FilePolarity,Negative*%
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW 7.0.10) date 2024-03-03 12:06:43*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G01*
|
||||
G04 APERTURE LIST*
|
||||
G04 Aperture macros list*
|
||||
%AMRoundRect*
|
||||
0 Rectangle with rounded corners*
|
||||
0 $1 Rounding radius*
|
||||
0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners*
|
||||
0 Add a 4 corners polygon primitive as box body*
|
||||
4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0*
|
||||
0 Add four circle primitives for the rounded corners*
|
||||
1,1,$1+$1,$2,$3*
|
||||
1,1,$1+$1,$4,$5*
|
||||
1,1,$1+$1,$6,$7*
|
||||
1,1,$1+$1,$8,$9*
|
||||
0 Add four rect primitives between the rounded corners*
|
||||
20,1,$1+$1,$2,$3,$4,$5,0*
|
||||
20,1,$1+$1,$4,$5,$6,$7,0*
|
||||
20,1,$1+$1,$6,$7,$8,$9,0*
|
||||
20,1,$1+$1,$8,$9,$2,$3,0*%
|
||||
G04 Aperture macros list end*
|
||||
%ADD10C,0.500000*%
|
||||
%ADD11R,3.500000X3.500000*%
|
||||
%ADD12RoundRect,0.750000X1.000000X-0.750000X1.000000X0.750000X-1.000000X0.750000X-1.000000X-0.750000X0*%
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%ADD13RoundRect,0.875000X0.875000X-0.875000X0.875000X0.875000X-0.875000X0.875000X-0.875000X-0.875000X0*%
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%ADD15RoundRect,0.250001X-0.949999X-0.949999X0.949999X-0.949999X0.949999X0.949999X-0.949999X0.949999X0*%
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||||
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%ADD20O,1.700000X1.700000*%
|
||||
%ADD21C,3.000000*%
|
||||
%ADD22C,1.600000*%
|
||||
%ADD23O,1.600000X1.600000*%
|
||||
G04 APERTURE END LIST*
|
||||
D10*
|
||||
%TO.C,KiKit_MB_9_2*%
|
||||
X50128000Y-46542666D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_4_6*%
|
||||
X80525333Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_4_2*%
|
||||
X33730666Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_8_4*%
|
||||
X55692000Y-35674143D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_7_4*%
|
||||
X50192000Y-21521334D03*
|
||||
%TD*%
|
||||
D11*
|
||||
%TO.C,J2*%
|
||||
X64192000Y-24500000D03*
|
||||
D12*
|
||||
X64192000Y-30500000D03*
|
||||
D13*
|
||||
X68892000Y-27500000D03*
|
||||
%TD*%
|
||||
D10*
|
||||
%TO.C,KiKit_MB_9_7*%
|
||||
X84692000Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_3_4*%
|
||||
X74192000Y-33000000D03*
|
||||
%TD*%
|
||||
D14*
|
||||
%TO.C,H2*%
|
||||
X94192000Y-4000000D03*
|
||||
%TD*%
|
||||
D10*
|
||||
%TO.C,KiKit_MB_9_3*%
|
||||
X81358666Y-35936000D03*
|
||||
%TD*%
|
||||
D14*
|
||||
%TO.C,H2*%
|
||||
X44064000Y-4000000D03*
|
||||
%TD*%
|
||||
D10*
|
||||
%TO.C,KiKit_MB_1_1*%
|
||||
X60692000Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_8_5*%
|
||||
X24897333Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_1_6*%
|
||||
X56525334Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_10_5*%
|
||||
X91025333Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_5_2*%
|
||||
X48128000Y-57053333D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_10_5*%
|
||||
X40897333Y-35936000D03*
|
||||
%TD*%
|
||||
D15*
|
||||
%TO.C,_J1*%
|
||||
X34064000Y-63500000D03*
|
||||
D16*
|
||||
X38024000Y-63500000D03*
|
||||
%TD*%
|
||||
D10*
|
||||
%TO.C,KiKit_MB_2_3*%
|
||||
X16897334Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_3_3*%
|
||||
X24897333Y-33000000D03*
|
||||
%TD*%
|
||||
D17*
|
||||
%TO.C,_D2*%
|
||||
X74192000Y-51250000D03*
|
||||
D18*
|
||||
X74192000Y-53790000D03*
|
||||
%TD*%
|
||||
D10*
|
||||
%TO.C,KiKit_MB_6_7*%
|
||||
X60692000Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_6_5*%
|
||||
X8897334Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_6_1*%
|
||||
X5564000Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_2_5*%
|
||||
X65358667Y-33000000D03*
|
||||
%TD*%
|
||||
D19*
|
||||
%TO.C,JPROG1*%
|
||||
X10668000Y-2349000D03*
|
||||
D20*
|
||||
X10668000Y-4889000D03*
|
||||
X10668000Y-7429000D03*
|
||||
%TD*%
|
||||
D21*
|
||||
%TO.C,_H2*%
|
||||
X94192000Y-40000000D03*
|
||||
%TD*%
|
||||
D10*
|
||||
%TO.C,KiKit_MB_10_2*%
|
||||
X88525333Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_9_4*%
|
||||
X50128000Y-44542666D03*
|
||||
%TD*%
|
||||
D15*
|
||||
%TO.C,J1*%
|
||||
X34064000Y-27500000D03*
|
||||
D16*
|
||||
X38024000Y-27500000D03*
|
||||
%TD*%
|
||||
D10*
|
||||
%TO.C,KiKit_MB_1_2*%
|
||||
X9730667Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_2_4*%
|
||||
X16064000Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_4_3*%
|
||||
X83025333Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_1_4*%
|
||||
X58192000Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_7_6*%
|
||||
X67858667Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_1_1*%
|
||||
X10564000Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_6_4*%
|
||||
X58192000Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_7_1*%
|
||||
X63692000Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_2_7*%
|
||||
X63692000Y-33000000D03*
|
||||
%TD*%
|
||||
D21*
|
||||
%TO.C,_H2*%
|
||||
X44064000Y-40000000D03*
|
||||
%TD*%
|
||||
D10*
|
||||
%TO.C,KiKit_MB_5_4*%
|
||||
X40064000Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_8_7*%
|
||||
X26564000Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_3_3*%
|
||||
X75025333Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_6_6*%
|
||||
X59858667Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_2_2*%
|
||||
X17730667Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_10_3*%
|
||||
X39230666Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_10_1*%
|
||||
X87692000Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_5_7*%
|
||||
X87692000Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_8_7*%
|
||||
X55692000Y-33032000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_1_7*%
|
||||
X5564000Y-33000000D03*
|
||||
%TD*%
|
||||
D14*
|
||||
%TO.C,H4*%
|
||||
X4064000Y-29000000D03*
|
||||
%TD*%
|
||||
D10*
|
||||
%TO.C,KiKit_MB_10_3*%
|
||||
X50128000Y-57053333D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_8_3*%
|
||||
X23230667Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_9_5*%
|
||||
X83025333Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_9_5*%
|
||||
X32897333Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_2_1*%
|
||||
X68692000Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_8_6*%
|
||||
X75858666Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_1_2*%
|
||||
X48064000Y-11010667D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_9_4*%
|
||||
X82192000Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_8_5*%
|
||||
X55692000Y-34793429D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_2_2*%
|
||||
X48064000Y-22521334D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_5_3*%
|
||||
X91025333Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_3_6*%
|
||||
X22397334Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_6_4*%
|
||||
X8064000Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_4_5*%
|
||||
X81358666Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_10_4*%
|
||||
X50128000Y-56053333D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_3_2*%
|
||||
X25730666Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_3_4*%
|
||||
X24064000Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_2_1*%
|
||||
X18564000Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_10_4*%
|
||||
X90192000Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_2_2*%
|
||||
X67858667Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_3_7*%
|
||||
X71692000Y-33000000D03*
|
||||
%TD*%
|
||||
D21*
|
||||
%TO.C,_H3*%
|
||||
X54192000Y-65000000D03*
|
||||
%TD*%
|
||||
D19*
|
||||
%TO.C,JSPK1*%
|
||||
X94792000Y-17724000D03*
|
||||
D20*
|
||||
X94792000Y-15184000D03*
|
||||
%TD*%
|
||||
D10*
|
||||
%TO.C,KiKit_MB_3_7*%
|
||||
X44937279Y-36032000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_1_2*%
|
||||
X59858667Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_6_1*%
|
||||
X55692000Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_3_7*%
|
||||
X21564000Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_4_4*%
|
||||
X32064000Y-33000000D03*
|
||||
%TD*%
|
||||
D11*
|
||||
%TO.C,_J2*%
|
||||
X14064000Y-60500000D03*
|
||||
D12*
|
||||
X14064000Y-66500000D03*
|
||||
D13*
|
||||
X18764000Y-63500000D03*
|
||||
%TD*%
|
||||
D10*
|
||||
%TO.C,KiKit_MB_7_6*%
|
||||
X17730667Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_6_7*%
|
||||
X10564000Y-35936000D03*
|
||||
%TD*%
|
||||
D17*
|
||||
%TO.C,_D2*%
|
||||
X24064000Y-51250000D03*
|
||||
D18*
|
||||
X24064000Y-53790000D03*
|
||||
%TD*%
|
||||
D10*
|
||||
%TO.C,KiKit_MB_7_3*%
|
||||
X65358667Y-35936000D03*
|
||||
%TD*%
|
||||
D21*
|
||||
%TO.C,_H1*%
|
||||
X4064000Y-40000000D03*
|
||||
%TD*%
|
||||
D10*
|
||||
%TO.C,KiKit_MB_1_6*%
|
||||
X6397334Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_5_4*%
|
||||
X90192000Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_8_7*%
|
||||
X76692000Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_1_3*%
|
||||
X48064000Y-12010667D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_3_2*%
|
||||
X42564000Y-33912715D03*
|
||||
%TD*%
|
||||
D14*
|
||||
%TO.C,H4*%
|
||||
X54192000Y-29000000D03*
|
||||
%TD*%
|
||||
D10*
|
||||
%TO.C,KiKit_MB_9_1*%
|
||||
X79692000Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_6_3*%
|
||||
X57358667Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_6_2*%
|
||||
X6397334Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_6_3*%
|
||||
X7230667Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_4_4*%
|
||||
X48128000Y-47542666D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_5_7*%
|
||||
X37564000Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_1_7*%
|
||||
X55692000Y-33000000D03*
|
||||
%TD*%
|
||||
D19*
|
||||
%TO.C,JPROG1*%
|
||||
X60796000Y-2349000D03*
|
||||
D20*
|
||||
X60796000Y-4889000D03*
|
||||
X60796000Y-7429000D03*
|
||||
%TD*%
|
||||
D10*
|
||||
%TO.C,KiKit_MB_4_3*%
|
||||
X32897333Y-33000000D03*
|
||||
%TD*%
|
||||
D22*
|
||||
%TO.C,_R1*%
|
||||
X61492000Y-44750000D03*
|
||||
D23*
|
||||
X86892000Y-44750000D03*
|
||||
%TD*%
|
||||
D10*
|
||||
%TO.C,KiKit_MB_8_1*%
|
||||
X21564000Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_1_4*%
|
||||
X48064000Y-13010667D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_10_2*%
|
||||
X38397333Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_5_6*%
|
||||
X38397333Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_3_2*%
|
||||
X75858666Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_8_3*%
|
||||
X55073141Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_9_7*%
|
||||
X34564000Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_8_3*%
|
||||
X73358667Y-35936000D03*
|
||||
%TD*%
|
||||
D11*
|
||||
%TO.C,_J2*%
|
||||
X64192000Y-60500000D03*
|
||||
D12*
|
||||
X64192000Y-66500000D03*
|
||||
D13*
|
||||
X68892000Y-63500000D03*
|
||||
%TD*%
|
||||
D10*
|
||||
%TO.C,KiKit_MB_7_2*%
|
||||
X50192000Y-23521334D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_1_5*%
|
||||
X57358667Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_2_4*%
|
||||
X66192000Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_7_3*%
|
||||
X50192000Y-22521334D03*
|
||||
%TD*%
|
||||
D21*
|
||||
%TO.C,_H1*%
|
||||
X54192000Y-40000000D03*
|
||||
%TD*%
|
||||
D14*
|
||||
%TO.C,H1*%
|
||||
X54192000Y-4000000D03*
|
||||
%TD*%
|
||||
D10*
|
||||
%TO.C,KiKit_MB_2_7*%
|
||||
X13564000Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_7_2*%
|
||||
X64525334Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_1_3*%
|
||||
X8897334Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_5_3*%
|
||||
X48128000Y-58053333D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_10_6*%
|
||||
X41730666Y-35936000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_7_1*%
|
||||
X50192000Y-24521334D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_5_3*%
|
||||
X40897333Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_1_5*%
|
||||
X7230667Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_1_3*%
|
||||
X59025334Y-33000000D03*
|
||||
%TD*%
|
||||
%TO.C,KiKit_MB_5_5*%
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Loading…
Reference in New Issue